From 8c89d50c10afdd98da82642ca5e9d7af4f1c18bd Mon Sep 17 00:00:00 2001 From: LIU Zhiwei Date: Mon, 13 Feb 2023 17:45:50 +0800 Subject: [PATCH] target/riscv: Fix vslide1up.vf and vslide1down.vf vslide1up_##BITWIDTH is used by the vslide1up.vx and vslide1up.vf. So its scalar input should be uint64_t to hold the 64 bits float register.And the same for vslide1down_##BITWIDTH. This bug is caught when run these instructions on qemu-riscv32. Signed-off-by: LIU Zhiwei Reviewed-by: Weiwei Li Reviewed-by: Frank Chang Message-ID: <20230213094550.29621-1-zhiwei_liu@linux.alibaba.com> Signed-off-by: Palmer Dabbelt --- target/riscv/vector_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 00de879787..3073c54871 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -5038,7 +5038,7 @@ GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4) GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8) #define GEN_VEXT_VSLIE1UP(BITWIDTH, H) \ -static void vslide1up_##BITWIDTH(void *vd, void *v0, target_ulong s1, \ +static void vslide1up_##BITWIDTH(void *vd, void *v0, uint64_t s1, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ typedef uint##BITWIDTH##_t ETYPE; \ @@ -5086,7 +5086,7 @@ GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, 32) GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, 64) #define GEN_VEXT_VSLIDE1DOWN(BITWIDTH, H) \ -static void vslide1down_##BITWIDTH(void *vd, void *v0, target_ulong s1, \ +static void vslide1down_##BITWIDTH(void *vd, void *v0, uint64_t s1, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ typedef uint##BITWIDTH##_t ETYPE; \