mirror of https://github.com/xemu-project/xemu.git
target/arm: Rename gen_exception_insn to gen_exception_insn_el
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220609202901.1177572-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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8c5d24dc7d
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@ -1161,9 +1161,9 @@ static bool fp_access_check(DisasContext *s)
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assert(!s->fp_access_checked);
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assert(!s->fp_access_checked);
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s->fp_access_checked = true;
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s->fp_access_checked = true;
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gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
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gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
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syn_fp_access_trap(1, 0xe, false, 0),
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syn_fp_access_trap(1, 0xe, false, 0),
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s->fp_excp_el);
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s->fp_excp_el);
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return false;
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return false;
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}
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}
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s->fp_access_checked = true;
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s->fp_access_checked = true;
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@ -1179,8 +1179,8 @@ bool sve_access_check(DisasContext *s)
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assert(!s->sve_access_checked);
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assert(!s->sve_access_checked);
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s->sve_access_checked = true;
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s->sve_access_checked = true;
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gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
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gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
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syn_sve_access_trap(), s->sve_excp_el);
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syn_sve_access_trap(), s->sve_excp_el);
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return false;
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return false;
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}
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}
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s->sve_access_checked = true;
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s->sve_access_checked = true;
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@ -1816,8 +1816,8 @@ static void gen_sysreg_undef(DisasContext *s, bool isread,
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} else {
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} else {
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syndrome = syn_uncategorized();
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syndrome = syn_uncategorized();
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}
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}
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gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syndrome,
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gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syndrome,
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default_exception_el(s));
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default_exception_el(s));
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}
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}
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/* MRS - move from system register
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/* MRS - move from system register
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@ -2069,8 +2069,8 @@ static void disas_exc(DisasContext *s, uint32_t insn)
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switch (op2_ll) {
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switch (op2_ll) {
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case 1: /* SVC */
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case 1: /* SVC */
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gen_ss_advance(s);
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gen_ss_advance(s);
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gen_exception_insn(s, s->base.pc_next, EXCP_SWI,
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gen_exception_insn_el(s, s->base.pc_next, EXCP_SWI,
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syn_aa64_svc(imm16), default_exception_el(s));
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syn_aa64_svc(imm16), default_exception_el(s));
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break;
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break;
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case 2: /* HVC */
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case 2: /* HVC */
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if (s->current_el == 0) {
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if (s->current_el == 0) {
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@ -2083,8 +2083,8 @@ static void disas_exc(DisasContext *s, uint32_t insn)
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gen_a64_set_pc_im(s->pc_curr);
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gen_a64_set_pc_im(s->pc_curr);
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gen_helper_pre_hvc(cpu_env);
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gen_helper_pre_hvc(cpu_env);
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gen_ss_advance(s);
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gen_ss_advance(s);
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gen_exception_insn(s, s->base.pc_next, EXCP_HVC,
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gen_exception_insn_el(s, s->base.pc_next, EXCP_HVC,
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syn_aa64_hvc(imm16), 2);
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syn_aa64_hvc(imm16), 2);
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break;
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break;
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case 3: /* SMC */
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case 3: /* SMC */
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if (s->current_el == 0) {
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if (s->current_el == 0) {
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@ -2094,8 +2094,8 @@ static void disas_exc(DisasContext *s, uint32_t insn)
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gen_a64_set_pc_im(s->pc_curr);
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gen_a64_set_pc_im(s->pc_curr);
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gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm16)));
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gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm16)));
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gen_ss_advance(s);
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gen_ss_advance(s);
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gen_exception_insn(s, s->base.pc_next, EXCP_SMC,
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gen_exception_insn_el(s, s->base.pc_next, EXCP_SMC,
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syn_aa64_smc(imm16), 3);
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syn_aa64_smc(imm16), 3);
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break;
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break;
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default:
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default:
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unallocated_encoding(s);
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unallocated_encoding(s);
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@ -14725,8 +14725,8 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
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* Illegal execution state. This has priority over BTI
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* Illegal execution state. This has priority over BTI
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* exceptions, but comes after instruction abort exceptions.
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* exceptions, but comes after instruction abort exceptions.
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*/
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*/
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gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
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gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
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syn_illegalstate(), default_exception_el(s));
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syn_illegalstate(), default_exception_el(s));
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return;
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return;
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}
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}
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@ -14757,9 +14757,9 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
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if (s->btype != 0
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if (s->btype != 0
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&& s->guarded_page
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&& s->guarded_page
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&& !btype_destination_ok(insn, s->bt, s->btype)) {
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&& !btype_destination_ok(insn, s->bt, s->btype)) {
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gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
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gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
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syn_btitrap(s->btype),
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syn_btitrap(s->btype),
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default_exception_el(s));
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default_exception_el(s));
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return;
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return;
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}
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}
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} else {
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} else {
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@ -143,8 +143,8 @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a)
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tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel);
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tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel);
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if (s->fp_excp_el != 0) {
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if (s->fp_excp_el != 0) {
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gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
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gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP,
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syn_uncategorized(), s->fp_excp_el);
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syn_uncategorized(), s->fp_excp_el);
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return true;
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return true;
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}
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}
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@ -376,7 +376,7 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
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if (!vfp_access_check_m(s, true)) {
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if (!vfp_access_check_m(s, true)) {
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/*
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/*
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* This was only a conditional exception, so override
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* This was only a conditional exception, so override
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* gen_exception_insn()'s default to DISAS_NORETURN
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* gen_exception_insn_el()'s default to DISAS_NORETURN
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*/
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*/
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s->base.is_jmp = DISAS_NEXT;
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s->base.is_jmp = DISAS_NEXT;
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break;
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break;
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@ -532,7 +532,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
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if (!vfp_access_check_m(s, true)) {
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if (!vfp_access_check_m(s, true)) {
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/*
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/*
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* This was only a conditional exception, so override
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* This was only a conditional exception, so override
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* gen_exception_insn()'s default to DISAS_NORETURN
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* gen_exception_insn_el()'s default to DISAS_NORETURN
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*/
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*/
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s->base.is_jmp = DISAS_NEXT;
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s->base.is_jmp = DISAS_NEXT;
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break;
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break;
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@ -765,14 +765,14 @@ static bool trans_NOCP(DisasContext *s, arg_nocp *a)
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}
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}
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if (a->cp != 10) {
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if (a->cp != 10) {
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gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
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gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP,
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syn_uncategorized(), default_exception_el(s));
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syn_uncategorized(), default_exception_el(s));
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return true;
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return true;
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}
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}
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if (s->fp_excp_el != 0) {
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if (s->fp_excp_el != 0) {
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gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
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gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP,
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syn_uncategorized(), s->fp_excp_el);
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syn_uncategorized(), s->fp_excp_el);
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return true;
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return true;
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}
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}
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@ -100,8 +100,8 @@ bool mve_eci_check(DisasContext *s)
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return true;
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return true;
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default:
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default:
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/* Reserved value: INVSTATE UsageFault */
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/* Reserved value: INVSTATE UsageFault */
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gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
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gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
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default_exception_el(s));
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default_exception_el(s));
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return false;
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return false;
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}
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}
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}
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}
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@ -230,7 +230,7 @@ static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled)
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int coproc = arm_dc_feature(s, ARM_FEATURE_V8) ? 0 : 0xa;
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int coproc = arm_dc_feature(s, ARM_FEATURE_V8) ? 0 : 0xa;
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uint32_t syn = syn_fp_access_trap(1, 0xe, false, coproc);
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uint32_t syn = syn_fp_access_trap(1, 0xe, false, coproc);
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gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn, s->fp_excp_el);
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gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syn, s->fp_excp_el);
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return false;
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return false;
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}
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}
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@ -260,8 +260,8 @@ bool vfp_access_check_m(DisasContext *s, bool skip_context_update)
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* the encoding space handled by the patterns in m-nocp.decode,
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* the encoding space handled by the patterns in m-nocp.decode,
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* and for them we may need to raise NOCP here.
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* and for them we may need to raise NOCP here.
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*/
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*/
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gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
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gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP,
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syn_uncategorized(), s->fp_excp_el);
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syn_uncategorized(), s->fp_excp_el);
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return false;
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return false;
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}
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}
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@ -1100,8 +1100,8 @@ static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp,
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s->base.is_jmp = DISAS_NORETURN;
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s->base.is_jmp = DISAS_NORETURN;
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}
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}
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void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
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void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp,
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uint32_t syn, uint32_t target_el)
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uint32_t syn, uint32_t target_el)
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{
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{
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gen_exception_insn_el_v(s, pc, excp, syn, tcg_constant_i32(target_el));
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gen_exception_insn_el_v(s, pc, excp, syn, tcg_constant_i32(target_el));
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}
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}
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@ -1117,8 +1117,8 @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
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void unallocated_encoding(DisasContext *s)
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void unallocated_encoding(DisasContext *s)
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{
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{
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/* Unallocated and reserved encodings are uncategorized */
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/* Unallocated and reserved encodings are uncategorized */
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gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
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gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
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default_exception_el(s));
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default_exception_el(s));
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}
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}
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/* Force a TB lookup after an instruction that changes the CPU state. */
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/* Force a TB lookup after an instruction that changes the CPU state. */
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@ -2869,8 +2869,8 @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
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undef:
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undef:
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/* If we get here then some access check did not pass */
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/* If we get here then some access check did not pass */
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gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
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gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
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syn_uncategorized(), exc_target);
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syn_uncategorized(), exc_target);
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return false;
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return false;
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}
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}
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@ -5094,7 +5094,8 @@ static void gen_srs(DisasContext *s,
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* For the UNPREDICTABLE cases we choose to UNDEF.
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* For the UNPREDICTABLE cases we choose to UNDEF.
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*/
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*/
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if (s->current_el == 1 && !s->ns && mode == ARM_CPU_MODE_MON) {
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if (s->current_el == 1 && !s->ns && mode == ARM_CPU_MODE_MON) {
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gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), 3);
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gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
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syn_uncategorized(), 3);
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return;
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return;
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}
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}
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@ -8479,8 +8480,8 @@ static bool trans_WLS(DisasContext *s, arg_WLS *a)
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* Do the check-and-raise-exception by hand.
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* Do the check-and-raise-exception by hand.
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*/
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*/
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if (s->fp_excp_el) {
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if (s->fp_excp_el) {
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gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
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gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP,
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syn_uncategorized(), s->fp_excp_el);
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syn_uncategorized(), s->fp_excp_el);
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return true;
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return true;
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}
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}
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}
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}
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@ -8582,8 +8583,8 @@ static bool trans_LE(DisasContext *s, arg_LE *a)
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tmp = load_cpu_field(v7m.ltpsize);
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tmp = load_cpu_field(v7m.ltpsize);
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tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc);
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tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc);
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tcg_temp_free_i32(tmp);
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tcg_temp_free_i32(tmp);
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gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
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gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
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default_exception_el(s));
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default_exception_el(s));
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gen_set_label(skipexc);
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gen_set_label(skipexc);
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}
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}
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@ -9053,8 +9054,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
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* UsageFault exception.
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* UsageFault exception.
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*/
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*/
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if (arm_dc_feature(s, ARM_FEATURE_M)) {
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if (arm_dc_feature(s, ARM_FEATURE_M)) {
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gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
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gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
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default_exception_el(s));
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default_exception_el(s));
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return;
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return;
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}
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}
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@ -9063,8 +9064,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
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* Illegal execution state. This has priority over BTI
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* Illegal execution state. This has priority over BTI
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* exceptions, but comes after instruction abort exceptions.
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* exceptions, but comes after instruction abort exceptions.
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*/
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*/
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gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
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gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
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syn_illegalstate(), default_exception_el(s));
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syn_illegalstate(), default_exception_el(s));
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return;
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return;
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}
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}
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@ -9633,8 +9634,8 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
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* Illegal execution state. This has priority over BTI
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* Illegal execution state. This has priority over BTI
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* exceptions, but comes after instruction abort exceptions.
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* exceptions, but comes after instruction abort exceptions.
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*/
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*/
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gen_exception_insn(dc, dc->pc_curr, EXCP_UDEF,
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gen_exception_insn_el(dc, dc->pc_curr, EXCP_UDEF,
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syn_illegalstate(), default_exception_el(dc));
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syn_illegalstate(), default_exception_el(dc));
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return;
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return;
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}
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}
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@ -9707,8 +9708,8 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
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*/
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*/
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tcg_remove_ops_after(dc->insn_eci_rewind);
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tcg_remove_ops_after(dc->insn_eci_rewind);
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dc->condjmp = 0;
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dc->condjmp = 0;
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gen_exception_insn(dc, dc->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
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gen_exception_insn_el(dc, dc->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
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default_exception_el(dc));
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default_exception_el(dc));
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}
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}
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arm_post_translate_insn(dc);
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arm_post_translate_insn(dc);
|
||||||
|
|
|
@ -279,8 +279,8 @@ void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
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||||||
void arm_gen_test_cc(int cc, TCGLabel *label);
|
void arm_gen_test_cc(int cc, TCGLabel *label);
|
||||||
MemOp pow2_align(unsigned i);
|
MemOp pow2_align(unsigned i);
|
||||||
void unallocated_encoding(DisasContext *s);
|
void unallocated_encoding(DisasContext *s);
|
||||||
void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
|
void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp,
|
||||||
uint32_t syn, uint32_t target_el);
|
uint32_t syn, uint32_t target_el);
|
||||||
|
|
||||||
/* Return state of Alternate Half-precision flag, caller frees result */
|
/* Return state of Alternate Half-precision flag, caller frees result */
|
||||||
static inline TCGv_i32 get_ahp_flag(void)
|
static inline TCGv_i32 get_ahp_flag(void)
|
||||||
|
|
Loading…
Reference in New Issue