ShuriZma
/
xemu
mirror of https://github.com/xemu-project/xemu.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

target/loongarch: Implement xvsrlr xvsrar 

This patch includes:
- XVSRLR[I].{B/H/W/D};
- XVSRAR[I].{B/H/W/D}.

Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914022645.1151356-38-gaosong@loongson.cn>
This commit is contained in:
Song Gao 2023-09-14 10:26:25 +08:00
parent 6567eac7f7
commit 8c272fe8f4
No known key found for this signature in database
GPG Key ID: 40A2FFF239263EDF
4 changed files with 59 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
target/loongarch/disas.c
View File

@ -2086,6 +2086,24 @@ INSN_LASX(xvsllwil_wu_hu, vv_i)
INSN_LASX(xvsllwil_du_wu, vv_i)
INSN_LASX(xvextl_qu_du, vv)
INSN_LASX(xvsrlr_b, vvv)
INSN_LASX(xvsrlr_h, vvv)
INSN_LASX(xvsrlr_w, vvv)
INSN_LASX(xvsrlr_d, vvv)
INSN_LASX(xvsrlri_b, vv_i)
INSN_LASX(xvsrlri_h, vv_i)
INSN_LASX(xvsrlri_w, vv_i)
INSN_LASX(xvsrlri_d, vv_i)
INSN_LASX(xvsrar_b, vvv)
INSN_LASX(xvsrar_h, vvv)
INSN_LASX(xvsrar_w, vvv)
INSN_LASX(xvsrar_d, vvv)
INSN_LASX(xvsrari_b, vv_i)
INSN_LASX(xvsrari_h, vv_i)
INSN_LASX(xvsrari_w, vv_i)
INSN_LASX(xvsrari_d, vv_i)
INSN_LASX(xvreplgr2vr_b, vr)
INSN_LASX(xvreplgr2vr_h, vr)
INSN_LASX(xvreplgr2vr_w, vr)

16
target/loongarch/insn_trans/trans_vec.c.inc
View File

@ -3739,6 +3739,14 @@ TRANS(vsrlri_b, LSX, gen_vv_i, gen_helper_vsrlri_b)
TRANS(vsrlri_h, LSX, gen_vv_i, gen_helper_vsrlri_h)
TRANS(vsrlri_w, LSX, gen_vv_i, gen_helper_vsrlri_w)
TRANS(vsrlri_d, LSX, gen_vv_i, gen_helper_vsrlri_d)
TRANS(xvsrlr_b, LASX, gen_xxx, gen_helper_vsrlr_b)
TRANS(xvsrlr_h, LASX, gen_xxx, gen_helper_vsrlr_h)
TRANS(xvsrlr_w, LASX, gen_xxx, gen_helper_vsrlr_w)
TRANS(xvsrlr_d, LASX, gen_xxx, gen_helper_vsrlr_d)
TRANS(xvsrlri_b, LASX, gen_xx_i, gen_helper_vsrlri_b)
TRANS(xvsrlri_h, LASX, gen_xx_i, gen_helper_vsrlri_h)
TRANS(xvsrlri_w, LASX, gen_xx_i, gen_helper_vsrlri_w)
TRANS(xvsrlri_d, LASX, gen_xx_i, gen_helper_vsrlri_d)
TRANS(vsrar_b, LSX, gen_vvv, gen_helper_vsrar_b)
TRANS(vsrar_h, LSX, gen_vvv, gen_helper_vsrar_h)
@ -3748,6 +3756,14 @@ TRANS(vsrari_b, LSX, gen_vv_i, gen_helper_vsrari_b)
TRANS(vsrari_h, LSX, gen_vv_i, gen_helper_vsrari_h)
TRANS(vsrari_w, LSX, gen_vv_i, gen_helper_vsrari_w)
TRANS(vsrari_d, LSX, gen_vv_i, gen_helper_vsrari_d)
TRANS(xvsrar_b, LASX, gen_xxx, gen_helper_vsrar_b)
TRANS(xvsrar_h, LASX, gen_xxx, gen_helper_vsrar_h)
TRANS(xvsrar_w, LASX, gen_xxx, gen_helper_vsrar_w)
TRANS(xvsrar_d, LASX, gen_xxx, gen_helper_vsrar_d)
TRANS(xvsrari_b, LASX, gen_xx_i, gen_helper_vsrari_b)
TRANS(xvsrari_h, LASX, gen_xx_i, gen_helper_vsrari_h)
TRANS(xvsrari_w, LASX, gen_xx_i, gen_helper_vsrari_w)
TRANS(xvsrari_d, LASX, gen_xx_i, gen_helper_vsrari_d)
TRANS(vsrln_b_h, LSX, gen_vvv, gen_helper_vsrln_b_h)
TRANS(vsrln_h_w, LSX, gen_vvv, gen_helper_vsrln_h_w)

17
target/loongarch/insns.decode
View File

@ -1661,6 +1661,23 @@ xvsllwil_wu_hu 0111 01110000 11000 1 .... ..... ..... @vv_ui4
xvsllwil_du_wu 0111 01110000 11001 ..... ..... ..... @vv_ui5
xvextl_qu_du 0111 01110000 11010 00000 ..... ..... @vv
xvsrlr_b 0111 01001111 00000 ..... ..... ..... @vvv
xvsrlr_h 0111 01001111 00001 ..... ..... ..... @vvv
xvsrlr_w 0111 01001111 00010 ..... ..... ..... @vvv
xvsrlr_d 0111 01001111 00011 ..... ..... ..... @vvv
xvsrlri_b 0111 01101010 01000 01 ... ..... ..... @vv_ui3
xvsrlri_h 0111 01101010 01000 1 .... ..... ..... @vv_ui4
xvsrlri_w 0111 01101010 01001 ..... ..... ..... @vv_ui5
xvsrlri_d 0111 01101010 0101 ...... ..... ..... @vv_ui6
xvsrar_b 0111 01001111 00100 ..... ..... ..... @vvv
xvsrar_h 0111 01001111 00101 ..... ..... ..... @vvv
xvsrar_w 0111 01001111 00110 ..... ..... ..... @vvv
xvsrar_d 0111 01001111 00111 ..... ..... ..... @vvv
xvsrari_b 0111 01101010 10000 01 ... ..... ..... @vv_ui3
xvsrari_h 0111 01101010 10000 1 .... ..... ..... @vv_ui4
xvsrari_w 0111 01101010 10001 ..... ..... ..... @vv_ui5
xvsrari_d 0111 01101010 1001 ...... ..... ..... @vv_ui6
xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr
xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr
xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr

12
target/loongarch/vec_helper.c
View File

@ -1025,8 +1025,9 @@ void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \
int oprsz = simd_oprsz(desc); \
\
for (i = 0; i < LSX_LEN/BIT; i++) { \
for (i = 0; i < oprsz / (BIT / 8); i++) { \
Vd->E(i) = do_vsrlr_ ## E(Vj->E(i), ((T)Vk->E(i))%BIT); \
} \
}
@ -1042,8 +1043,9 @@ void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
int i; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
int oprsz = simd_oprsz(desc); \
\
for (i = 0; i < LSX_LEN/BIT; i++) { \
for (i = 0; i < oprsz / (BIT / 8); i++) { \
Vd->E(i) = do_vsrlr_ ## E(Vj->E(i), imm); \
} \
}
@ -1075,8 +1077,9 @@ void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \
int oprsz = simd_oprsz(desc); \
\
for (i = 0; i < LSX_LEN/BIT; i++) { \
for (i = 0; i < oprsz / (BIT / 8); i++) { \
Vd->E(i) = do_vsrar_ ## E(Vj->E(i), ((T)Vk->E(i))%BIT); \
} \
}
@ -1092,8 +1095,9 @@ void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
int i; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
int oprsz = simd_oprsz(desc); \
\
for (i = 0; i < LSX_LEN/BIT; i++) { \
for (i = 0; i < oprsz / (BIT / 8); i++) { \
Vd->E(i) = do_vsrar_ ## E(Vj->E(i), imm); \
} \
}