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target/tricore: Use tcg_gen_*extract_tl 

The EXTR instructions can use the extract opcodes.

Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-10-19 11:23:19 -07:00
parent 0d67249c6d
commit 8b8bb29548
1 changed files with 4 additions and 16 deletions
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18
target/tricore/translate.c
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@ -6543,27 +6543,15 @@ static void decode_rrpw_extract_insert(DisasContext *ctx)
case OPC2_32_RRPW_EXTR: case OPC2_32_RRPW_EXTR:
if (width == 0) { if (width == 0) {
tcg_gen_movi_tl(cpu_gpr_d[r3], 0); tcg_gen_movi_tl(cpu_gpr_d[r3], 0);
break; } else if (pos + width <= 32) {
} tcg_gen_sextract_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos, width);
if (pos + width <= 32) {
/* optimize special cases */
if ((pos == 0) && (width == 8)) {
tcg_gen_ext8s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
} else if ((pos == 0) && (width == 16)) {
tcg_gen_ext16s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
} else {
tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32 - pos - width);
tcg_gen_sari_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32 - width);
}
} }
break; break;
case OPC2_32_RRPW_EXTR_U: case OPC2_32_RRPW_EXTR_U:
if (width == 0) { if (width == 0) {
tcg_gen_movi_tl(cpu_gpr_d[r3], 0); tcg_gen_movi_tl(cpu_gpr_d[r3], 0);
} else { } else {
tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos); tcg_gen_extract_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos, width);
tcg_gen_andi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], ~0u >> (32-width));
} }
break; break;
case OPC2_32_RRPW_IMASK: case OPC2_32_RRPW_IMASK: