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MIPS patches queue 

- Various TCG fixes (Marcin Nowakowski, Ni Hui, Stefan Pejic, Stefan Pejic)
 - Sysbus floppy controller fix (Peter Maydell)
 - QOM'ification of PIIX southbridge (Mark Cave-Ayland, Bernhard Beschow)
 - Various fixes on ISA devices commonly used by x86/mips machines (Bernhard)
 - Few cleanups in accel/tcg & documentation (Bernhard)
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Merge tag 'mips-20220611' of https://github.com/philmd/qemu into staging

MIPS patches queue

- Various TCG fixes (Marcin Nowakowski, Ni Hui, Stefan Pejic, Stefan Pejic)
- Sysbus floppy controller fix (Peter Maydell)
- QOM'ification of PIIX southbridge (Mark Cave-Ayland, Bernhard Beschow)
- Various fixes on ISA devices commonly used by x86/mips machines (Bernhard)
- Few cleanups in accel/tcg & documentation (Bernhard)

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# gpg: Signature made Sat 11 Jun 2022 03:30:41 AM PDT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]

* tag 'mips-20220611' of https://github.com/philmd/qemu: (49 commits)
  docs/devel: Fix link to developer mailing lists
  accel/tcg: Inline dump_opcount_info() and remove it
  accel/tcg/cpu-exec: Unexport dump_drift_info()
  hw/net/fsl_etsec/etsec: Remove obsolete and unused etsec_create()
  hw/i386/pc: Remove orphan declarations
  hw/i386/pc: Unexport functions used only internally
  hw/i386/pc: Unexport PC_CPU_MODEL_IDS macro
  hw/audio/cs4231a: Const'ify global tables
  hw: Reuse TYPE_I8042 define
  hw/rtc/mc146818rtc: QOM'ify io_base offset
  hw/i386/microvm-dt: Determine mc146818rtc's IRQ number from QOM property
  hw/i386/microvm-dt: Force explicit failure if retrieving QOM property fails
  hw/isa/piix3: Inline and remove piix3_create()
  hw/isa/piix3: Factor out ISABus retrieval from piix3_create()
  hw/isa/piix3: QOM'ify PCI device creation and wiring
  hw/isa/piix3: Move pci_map_irq_fn near pci_set_irq_fn
  hw/isa/piix4: Inline and remove piix4_create()
  hw/isa/piix4: QOM'ify PIIX4 PM creation
  hw/isa/piix4: Factor out ISABus retrieval from piix4_create()
  hw/isa/piix4: QOM'ify PCI device creation and wiring
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-06-11 08:18:55 -07:00
parent 30796f5567 37da3bcf01
commit 8b7f856e9d
34 changed files with 333 additions and 320 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
MAINTAINERS
View File

@ -246,7 +246,8 @@ F: docs/system/cpu-models-mips.rst.inc
F: tests/tcg/mips/
MIPS TCG CPUs (nanoMIPS ISA)
S: Orphan
M: Stefan Pejic <stefan.pejic@syrmia.com>
S: Maintained
F: disas/nanomips.*
F: target/mips/tcg/*nanomips*

4
accel/tcg/cpu-exec.c
View File

@ -1048,7 +1048,7 @@ void tcg_exec_unrealizefn(CPUState *cpu)
#ifndef CONFIG_USER_ONLY
void dump_drift_info(GString *buf)
static void dump_drift_info(GString *buf)
{
if (!icount_enabled()) {
return;
@ -1091,7 +1091,7 @@ HumanReadableText *qmp_x_query_opcount(Error **errp)
return NULL;
}
dump_opcount_info(buf);
tcg_dump_op_count(buf);
return human_readable_text_from_str(buf);
}

5
accel/tcg/translate-all.c
View File

@ -2124,11 +2124,6 @@ void dump_exec_info(GString *buf)
tcg_dump_info(buf);
}
void dump_opcount_info(GString *buf)
{
tcg_dump_op_count(buf);
}
#else /* CONFIG_USER_ONLY */
void cpu_interrupt(CPUState *cpu, int mask)

30
docs/about/deprecated.rst
View File

@ -213,17 +213,6 @@ MIPS ``Trap-and-Emul`` KVM support (since 6.0)
The MIPS ``Trap-and-Emul`` KVM host and guest support has been removed
from Linux upstream kernel, declare it deprecated.
System emulator CPUS
--------------------
MIPS ``I7200`` CPU Model (since 5.2)
''''''''''''''''''''''''''''''''''''
The ``I7200`` guest CPU relies on the nanoMIPS ISA, which is deprecated
(the ISA has never been upstreamed to a compiler toolchain). Therefore
this CPU is also deprecated.
QEMU API (QAPI) events
----------------------
@ -337,16 +326,6 @@ The above, converted to the current supported format::
json:{"file.driver":"rbd", "file.pool":"rbd", "file.image":"name"}
linux-user mode CPUs
--------------------
MIPS ``I7200`` CPU (since 5.2)
''''''''''''''''''''''''''''''
The ``I7200`` guest CPU relies on the nanoMIPS ISA, which is deprecated
(the ISA has never been upstreamed to a compiler toolchain). Therefore
this CPU is also deprecated.
Backwards compatibility
-----------------------
@ -376,15 +355,6 @@ versions, aliases will point to newer CPU model versions
depending on the machine type, so management software must
resolve CPU model aliases before starting a virtual machine.
Guest Emulator ISAs
-------------------
nanoMIPS ISA
''''''''''''
The ``nanoMIPS`` ISA has never been upstreamed to any compiler toolchain.
As it is hard to generate binaries for it, declare it deprecated.
Tools
-----

6
docs/devel/submitting-a-patch.rst
View File

@ -18,9 +18,9 @@ one-shot fix, the bare minimum we ask is that:
<http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/SubmittingPatches?id=f6f94e2ab1b33f0082ac22d71f66385a60d8157f#n297>`__
policy.) ``git commit -s`` or ``git format-patch -s`` will add one.
- All contributions to QEMU must be **sent as patches** to the
qemu-devel `mailing list <MailingLists>`__. Patch contributions
should not be posted on the bug tracker, posted on forums, or
externally hosted and linked to. (We have other mailing lists too,
qemu-devel `mailing list <https://wiki.qemu.org/Contribute/MailingLists>`__.
Patch contributions should not be posted on the bug tracker, posted on
forums, or externally hosted and linked to. (We have other mailing lists too,
but all patches must go to qemu-devel, possibly with a Cc: to another
list.) ``git send-email`` (`step-by-step setup
guide <https://git-send-email.io/>`__ and `hints and

77
hw/acpi/piix4.c
View File

@ -28,6 +28,8 @@
#include "hw/pci/pci.h"
#include "hw/qdev-properties.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/pcihp.h"
#include "hw/acpi/piix4.h"
#include "sysemu/runstate.h"
#include "sysemu/sysemu.h"
#include "sysemu/xen.h"
@ -56,47 +58,6 @@ struct pci_status {
uint32_t down;
};
struct PIIX4PMState {
/*< private >*/
PCIDevice parent_obj;
/*< public >*/
MemoryRegion io;
uint32_t io_base;
MemoryRegion io_gpe;
ACPIREGS ar;
APMState apm;
PMSMBus smb;
uint32_t smb_io_base;
qemu_irq irq;
qemu_irq smi_irq;
int smm_enabled;
bool smm_compat;
Notifier machine_ready;
Notifier powerdown_notifier;
AcpiPciHpState acpi_pci_hotplug;
bool use_acpi_hotplug_bridge;
bool use_acpi_root_pci_hotplug;
bool not_migrate_acpi_index;
uint8_t disable_s3;
uint8_t disable_s4;
uint8_t s4_val;
bool cpu_hotplug_legacy;
AcpiCpuHotplug gpe_cpu;
CPUHotplugState cpuhp_state;
MemHotplugState acpi_memory_hotplug;
};
OBJECT_DECLARE_SIMPLE_TYPE(PIIX4PMState, PIIX4_PM)
static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
PCIBus *bus, PIIX4PMState *s);
@ -525,6 +486,10 @@ static void piix4_pm_realize(PCIDevice *dev, Error **errp)
s->machine_ready.notify = piix4_pm_machine_ready;
qemu_add_machine_init_done_notifier(&s->machine_ready);
if (xen_enabled()) {
s->use_acpi_hotplug_bridge = false;
}
piix4_acpi_system_hot_add_init(pci_address_space_io(dev),
pci_get_bus(dev), s);
qbus_set_hotplug_handler(BUS(pci_get_bus(dev)), OBJECT(s));
@ -532,32 +497,12 @@ static void piix4_pm_realize(PCIDevice *dev, Error **errp)
piix4_pm_add_properties(s);
}
I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
qemu_irq sci_irq, qemu_irq smi_irq,
int smm_enabled, DeviceState **piix4_pm)
static void piix4_pm_init(Object *obj)
{
PCIDevice *pci_dev;
DeviceState *dev;
PIIX4PMState *s;
PIIX4PMState *s = PIIX4_PM(obj);
pci_dev = pci_new(devfn, TYPE_PIIX4_PM);
dev = DEVICE(pci_dev);
qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base);
if (piix4_pm) {
*piix4_pm = dev;
}
s = PIIX4_PM(dev);
s->irq = sci_irq;
s->smi_irq = smi_irq;
s->smm_enabled = smm_enabled;
if (xen_enabled()) {
s->use_acpi_hotplug_bridge = false;
}
pci_realize_and_unref(pci_dev, bus, &error_fatal);
return s->smb.smbus;
qdev_init_gpio_out(DEVICE(obj), &s->irq, 1);
qdev_init_gpio_out_named(DEVICE(obj), &s->smi_irq, "smi-irq", 1);
}
static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
@ -663,6 +608,7 @@ static Property piix4_pm_properties[] = {
DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState,
acpi_memory_hotplug.is_enabled, true),
DEFINE_PROP_BOOL("smm-compat", PIIX4PMState, smm_compat, false),
DEFINE_PROP_BOOL("smm-enabled", PIIX4PMState, smm_enabled, false),
DEFINE_PROP_BOOL("x-not-migrate-acpi-index", PIIX4PMState,
not_migrate_acpi_index, false),
DEFINE_PROP_END_OF_LIST(),
@ -703,6 +649,7 @@ static void piix4_pm_class_init(ObjectClass *klass, void *data)
static const TypeInfo piix4_pm_info = {
.name = TYPE_PIIX4_PM,
.parent = TYPE_PCI_DEVICE,
.instance_init = piix4_pm_init,
.instance_size = sizeof(PIIX4PMState),
.class_init = piix4_pm_class_init,
.interfaces = (InterfaceInfo[]) {

8
hw/audio/cs4231a.c
View File

@ -84,7 +84,7 @@ struct CSState {
int transferred;
int aci_counter;
SWVoiceOut *voice;
int16_t *tab;
const int16_t *tab;
};
#define MODE2 (1 << 6)
@ -142,13 +142,13 @@ enum {
Capture_Lower_Base_Count
};
static int freqs[2][8] = {
static const int freqs[2][8] = {
{ 8000, 16000, 27420, 32000, -1, -1, 48000, 9000 },
{ 5510, 11025, 18900, 22050, 37800, 44100, 33075, 6620 }
};
/* Tables courtesy http://hazelware.luggle.com/tutorials/mulawcompression.html */
static int16_t MuLawDecompressTable[256] =
static const int16_t MuLawDecompressTable[256] =
{
-32124,-31100,-30076,-29052,-28028,-27004,-25980,-24956,
-23932,-22908,-21884,-20860,-19836,-18812,-17788,-16764,
@ -184,7 +184,7 @@ static int16_t MuLawDecompressTable[256] =
56, 48, 40, 32, 24, 16, 8, 0
};
static int16_t ALawDecompressTable[256] =
static const int16_t ALawDecompressTable[256] =
{
-5504, -5248, -6016, -5760, -4480, -4224, -4992, -4736,
-7552, -7296, -8064, -7808, -6528, -6272, -7040, -6784,

16
hw/block/fdc-sysbus.c
View File

@ -94,18 +94,14 @@ static void fdctrl_handle_tc(void *opaque, int irq, int level)
trace_fdctrl_tc_pulse(level);
}
void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
hwaddr mmio_base, DriveInfo **fds)
void fdctrl_init_sysbus(qemu_irq irq, hwaddr mmio_base, DriveInfo **fds)
{
FDCtrl *fdctrl;
DeviceState *dev;
SysBusDevice *sbd;
FDCtrlSysBus *sys;
dev = qdev_new("sysbus-fdc");
sys = SYSBUS_FDC(dev);
fdctrl = &sys->state;
fdctrl->dma_chann = dma_chann; /* FIXME */
sbd = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(sbd, &error_fatal);
sysbus_connect_irq(sbd, 0, irq);
@ -138,6 +134,16 @@ static void sysbus_fdc_common_instance_init(Object *obj)
FDCtrlSysBus *sys = SYSBUS_FDC(obj);
FDCtrl *fdctrl = &sys->state;
/*
* DMA is not currently supported for sysbus floppy controllers.
* If we wanted to add support then probably the best approach is
* to have a QOM link property 'dma-controller' which the board
* code can set to an instance of IsaDmaClass, and an integer
* property 'dma-channel', so that we can set fdctrl->dma and
* fdctrl->dma_chann accordingly.
*/
fdctrl->dma_chann = -1;
qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */
memory_region_init_io(&fdctrl->iomem, obj,

1
hw/i386/acpi-build.c
View File

@ -44,6 +44,7 @@
#include "hw/acpi/tpm.h"
#include "hw/acpi/vmgenid.h"
#include "hw/acpi/erst.h"
#include "hw/acpi/piix4.h"
#include "sysemu/tpm_backend.h"
#include "hw/rtc/mc146818rtc_regs.h"
#include "migration/vmstate.h"

9
hw/i386/microvm-dt.c
View File

@ -32,6 +32,7 @@
*/
#include "qemu/osdep.h"
#include "qemu/cutils.h"
#include "qapi/error.h"
#include "sysemu/device_tree.h"
#include "hw/char/serial.h"
#include "hw/i386/fw_cfg.h"
@ -187,8 +188,8 @@ static void dt_add_ioapic(MicrovmMachineState *mms, SysBusDevice *dev)
static void dt_add_isa_serial(MicrovmMachineState *mms, ISADevice *dev)
{
const char compat[] = "ns16550";
uint32_t irq = object_property_get_int(OBJECT(dev), "irq", NULL);
hwaddr base = object_property_get_int(OBJECT(dev), "iobase", NULL);
uint32_t irq = object_property_get_int(OBJECT(dev), "irq", &error_fatal);
hwaddr base = object_property_get_int(OBJECT(dev), "iobase", &error_fatal);
hwaddr size = 8;
char *nodename;
@ -208,8 +209,8 @@ static void dt_add_isa_serial(MicrovmMachineState *mms, ISADevice *dev)
static void dt_add_isa_rtc(MicrovmMachineState *mms, ISADevice *dev)
{
const char compat[] = "motorola,mc146818";
uint32_t irq = RTC_ISA_IRQ;
hwaddr base = RTC_ISA_BASE;
uint32_t irq = object_property_get_uint(OBJECT(dev), "irq", &error_fatal);
hwaddr base = object_property_get_uint(OBJECT(dev), "iobase", &error_fatal);
hwaddr size = 8;
char *nodename;

17
hw/i386/pc.c
View File

@ -98,6 +98,15 @@
#include "trace.h"
#include CONFIG_DEVICES
/*
* Helper for setting model-id for CPU models that changed model-id
* depending on QEMU versions up to QEMU 2.4.
*/
#define PC_CPU_MODEL_IDS(v) \
{ "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
{ "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
{ "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
GlobalProperty pc_compat_7_0[] = {};
const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0);
@ -563,7 +572,7 @@ static const char * const fdc_container_path[] = {
* Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
* and ACPI objects.
*/
ISADevice *pc_find_fdc0(void)
static ISADevice *pc_find_fdc0(void)
{
int i;
Object *container;
@ -707,7 +716,7 @@ static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
0x280, 0x380 };
static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
static void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
{
static int nb_ne2k = 0;
@ -1097,7 +1106,7 @@ static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl,
return;
}
i8042 = isa_create_simple(isa_bus, "i8042");
i8042 = isa_create_simple(isa_bus, TYPE_I8042);
if (!no_vmport) {
isa_create_simple(isa_bus, TYPE_VMPORT);
vmmouse = isa_try_new("vmmouse");
@ -1105,7 +1114,7 @@ static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl,
vmmouse = NULL;
}
if (vmmouse) {
object_property_set_link(OBJECT(vmmouse), "i8042", OBJECT(i8042),
object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042),
&error_abort);
isa_realize_and_unref(vmmouse, isa_bus, &error_fatal);
}

23
hw/i386/pc_piix.c
View File

@ -47,6 +47,7 @@
#include "hw/xen/xen-x86.h"
#include "exec/memory.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/piix4.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "sysemu/xen.h"
@ -196,6 +197,9 @@ static void pc_init1(MachineState *machine,
if (pcmc->pci_enabled) {
PIIX3State *piix3;
PCIDevice *pci_dev;
const char *type = xen_enabled() ? TYPE_PIIX3_XEN_DEVICE
: TYPE_PIIX3_DEVICE;
pci_bus = i440fx_init(host_type,
pci_type,
@ -206,9 +210,11 @@ static void pc_init1(MachineState *machine,
pci_memory, ram_memory);
pcms->bus = pci_bus;
piix3 = piix3_create(pci_bus, &isa_bus);
pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, type);
piix3 = PIIX3_PCI_DEVICE(pci_dev);
piix3->pic = x86ms->gsi;
piix3_devfn = piix3->dev.devfn;
isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
} else {
pci_bus = NULL;
i440fx_state = NULL;
@ -280,14 +286,19 @@ static void pc_init1(MachineState *machine,
}
if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
DeviceState *piix4_pm;
PCIDevice *piix4_pm;
smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0);
piix4_pm = pci_new(piix3_devfn + 3, TYPE_PIIX4_PM);
qdev_prop_set_uint32(DEVICE(piix4_pm), "smb_io_base", 0xb100);
qdev_prop_set_bit(DEVICE(piix4_pm), "smm-enabled",
x86_machine_is_smm_enabled(x86ms));
pci_realize_and_unref(piix4_pm, pci_bus, &error_fatal);
qdev_connect_gpio_out(DEVICE(piix4_pm), 0, x86ms->gsi[9]);
qdev_connect_gpio_out_named(DEVICE(piix4_pm), "smi-irq", 0, smi_irq);
pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(piix4_pm), "i2c"));
/* TODO: Populate SPD eeprom data. */
pcms->smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
x86ms->gsi[9], smi_irq,
x86_machine_is_smm_enabled(x86ms),
&piix4_pm);
smbus_eeprom_init(pcms->smbus, 8, NULL, 0);
object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,

98
hw/isa/piix3.c
View File

@ -24,6 +24,7 @@
#include "qemu/osdep.h"
#include "qemu/range.h"
#include "qapi/error.h"
#include "hw/southbridge/piix.h"
#include "hw/irq.h"
#include "hw/isa/isa.h"
@ -36,9 +37,6 @@
#define XEN_PIIX_NUM_PIRQS 128ULL
#define TYPE_PIIX3_DEVICE "PIIX3"
#define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen"
static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
{
qemu_set_irq(piix3->pic[pic_irq],
@ -82,6 +80,17 @@ static void piix3_set_irq(void *opaque, int pirq, int level)
piix3_set_irq_level(piix3, pirq, level);
}
/*
* Return the global irq number corresponding to a given device irq
* pin. We could also use the bus number to have a more precise mapping.
*/
static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
{
int slot_addend;
slot_addend = PCI_SLOT(pci_dev->devfn) - 1;
return (pci_intx + slot_addend) & 3;
}
static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
{
PIIX3State *piix3 = opaque;
@ -270,7 +279,7 @@ static const MemoryRegionOps rcr_ops = {
.endianness = DEVICE_LITTLE_ENDIAN
};
static void piix3_realize(PCIDevice *dev, Error **errp)
static void pci_piix3_realize(PCIDevice *dev, Error **errp)
{
PIIX3State *d = PIIX3_PCI_DEVICE(dev);
@ -309,7 +318,6 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data)
dc->desc = "ISA bridge";
dc->vmsd = &vmstate_piix3;
dc->hotpluggable = false;
k->realize = piix3_realize;
k->vendor_id = PCI_VENDOR_ID_INTEL;
/* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
@ -335,11 +343,28 @@ static const TypeInfo piix3_pci_type_info = {
},
};
static void piix3_realize(PCIDevice *dev, Error **errp)
{
ERRP_GUARD();
PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
PCIBus *pci_bus = pci_get_bus(dev);
pci_piix3_realize(dev, errp);
if (*errp) {
return;
}
pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
piix3, PIIX_NUM_PIRQS);
pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
};
static void piix3_class_init(ObjectClass *klass, void *data)
{
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->config_write = piix3_write_config;
k->realize = piix3_realize;
}
static const TypeInfo piix3_info = {
@ -348,11 +373,33 @@ static const TypeInfo piix3_info = {
.class_init = piix3_class_init,
};
static void piix3_xen_realize(PCIDevice *dev, Error **errp)
{
ERRP_GUARD();
PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
PCIBus *pci_bus = pci_get_bus(dev);
pci_piix3_realize(dev, errp);
if (*errp) {
return;
}
/*
* Xen supports additional interrupt routes from the PCI devices to
* the IOAPIC: the four pins of each PCI device on the bus are also
* connected to the IOAPIC directly.
* These additional routes can be discovered through ACPI.
*/
pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
piix3, XEN_PIIX_NUM_PIRQS);
};
static void piix3_xen_class_init(ObjectClass *klass, void *data)
{
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->config_write = piix3_write_config_xen;
k->realize = piix3_xen_realize;
};
static const TypeInfo piix3_xen_info = {
@ -369,44 +416,3 @@ static void piix3_register_types(void)
}
type_init(piix3_register_types)
/*
* Return the global irq number corresponding to a given device irq
* pin. We could also use the bus number to have a more precise mapping.
*/
static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
{
int slot_addend;
slot_addend = PCI_SLOT(pci_dev->devfn) - 1;
return (pci_intx + slot_addend) & 3;
}
PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
{
PIIX3State *piix3;
PCIDevice *pci_dev;
/*
* Xen supports additional interrupt routes from the PCI devices to
* the IOAPIC: the four pins of each PCI device on the bus are also
* connected to the IOAPIC directly.
* These additional routes can be discovered through ACPI.
*/
if (xen_enabled()) {
pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
TYPE_PIIX3_XEN_DEVICE);
piix3 = PIIX3_PCI_DEVICE(pci_dev);
pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
piix3, XEN_PIIX_NUM_PIRQS);
} else {
pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
TYPE_PIIX3_DEVICE);
piix3 = PIIX3_PCI_DEVICE(pci_dev);
pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
piix3, PIIX_NUM_PIRQS);
pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
}
*isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
return piix3;
}

116
hw/isa/piix4.c
View File

@ -34,6 +34,8 @@
#include "hw/timer/i8254.h"
#include "hw/rtc/mc146818rtc.h"
#include "hw/ide/pci.h"
#include "hw/acpi/piix4.h"
#include "hw/usb/hcd-uhci.h"
#include "migration/vmstate.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"
@ -45,6 +47,9 @@ struct PIIX4State {
qemu_irq *isa;
RTCState rtc;
PCIIDEState ide;
UHCIState uhci;
PIIX4PMState pm;
/* Reset Control Register */
MemoryRegion rcr_mem;
uint8_t rcr;
@ -73,6 +78,31 @@ static void piix4_set_irq(void *opaque, int irq_num, int level)
}
}
static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
{
int slot;
slot = PCI_SLOT(pci_dev->devfn);
switch (slot) {
/* PIIX4 USB */
case 10:
return 3;
/* AMD 79C973 Ethernet */
case 11:
return 1;
/* Crystal 4281 Sound */
case 12:
return 2;
/* PCI slot 1 to 4 */
case 18 ... 21:
return ((slot - 18) + irq_num) & 0x03;
/* Unknown device, don't do any translation */
default:
return irq_num;
}
}
static void piix4_isa_reset(DeviceState *dev)
{
PIIX4State *d = PIIX4_PCI_DEVICE(dev);
@ -179,6 +209,7 @@ static const MemoryRegionOps piix4_rcr_ops = {
static void piix4_realize(PCIDevice *dev, Error **errp)
{
PIIX4State *s = PIIX4_PCI_DEVICE(dev);
PCIBus *pci_bus = pci_get_bus(dev);
ISABus *isa_bus;
qemu_irq *i8259_out_irq;
@ -217,13 +248,41 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
return;
}
s->rtc.irq = isa_get_irq(ISA_DEVICE(&s->rtc), s->rtc.isairq);
/* IDE */
qdev_prop_set_int32(DEVICE(&s->ide), "addr", dev->devfn + 1);
if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) {
return;
}
pci_ide_create_devs(PCI_DEVICE(&s->ide));
/* USB */
qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2);
if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) {
return;
}
/* ACPI controller */
qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3);
if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) {
return;
}
qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa[9]);
pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS);
}
static void piix4_init(Object *obj)
{
PIIX4State *s = PIIX4_PCI_DEVICE(obj);
object_initialize(&s->rtc, sizeof(s->rtc), TYPE_MC146818_RTC);
object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC);
object_initialize_child(obj, "ide", &s->ide, "piix4-ide");
object_initialize_child(obj, "uhci", &s->uhci, "piix4-usb-uhci");
object_initialize_child(obj, "pm", &s->pm, TYPE_PIIX4_PM);
qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", 0x1100);
qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", 0);
}
static void piix4_class_init(ObjectClass *klass, void *data)
@ -264,58 +323,3 @@ static void piix4_register_types(void)
}
type_init(piix4_register_types)
static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
{
int slot;
slot = PCI_SLOT(pci_dev->devfn);
switch (slot) {
/* PIIX4 USB */
case 10:
return 3;
/* AMD 79C973 Ethernet */
case 11:
return 1;
/* Crystal 4281 Sound */
case 12:
return 2;
/* PCI slot 1 to 4 */
case 18 ... 21:
return ((slot - 18) + irq_num) & 0x03;
/* Unknown device, don't do any translation */
default:
return irq_num;
}
}
DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
{
PIIX4State *s;
PCIDevice *pci;
DeviceState *dev;
int devfn = PCI_DEVFN(10, 0);
pci = pci_create_simple_multifunction(pci_bus, devfn, true,
TYPE_PIIX4_PCI_DEVICE);
dev = DEVICE(pci);
s = PIIX4_PCI_DEVICE(pci);
if (isa_bus) {
*isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
}
pci = pci_create_simple(pci_bus, devfn + 1, "piix4-ide");
pci_ide_create_devs(pci);
pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci");
if (smbus) {
*smbus = piix4_pm_init(pci_bus, devfn + 3, 0x1100,
qdev_get_gpio_in_named(dev, "isa", 9),
NULL, 0, NULL);
}
pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS);
return dev;
}

2
hw/mips/jazz.c
View File

@ -353,7 +353,7 @@ static void mips_jazz_init(MachineState *machine,
fds[n] = drive_get(IF_FLOPPY, 0, n);
}
/* FIXME: we should enable DMA with a custom IsaDma device */
fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), -1, 0x80003000, fds);
fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), 0x80003000, fds);
/* Real time clock */
mc146818_rtc_init(isa_bus, 1980, NULL);

9
hw/mips/malta.c
View File

@ -1237,7 +1237,9 @@ void mips_malta_init(MachineState *machine)
int fl_idx = 0;
int be;
MaltaState *s;
PCIDevice *piix4;
DeviceState *dev;
DeviceState *pm_dev;
s = MIPS_MALTA(qdev_new(TYPE_MIPS_MALTA));
sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal);
@ -1399,7 +1401,12 @@ void mips_malta_init(MachineState *machine)
empty_slot_init("GT64120", 0, 0x20000000);
/* Southbridge */
dev = piix4_create(pci_bus, &isa_bus, &smbus);
piix4 = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), true,
TYPE_PIIX4_PCI_DEVICE);
dev = DEVICE(piix4);
isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
pm_dev = DEVICE(object_resolve_path_component(OBJECT(dev), "pm"));
smbus = I2C_BUS(qdev_get_child_bus(pm_dev, "i2c"));
/* Interrupt controller */
qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);

23
hw/net/fsl_etsec/etsec.c
View File

@ -443,26 +443,3 @@ static void etsec_register_types(void)
}
type_init(etsec_register_types)
DeviceState *etsec_create(hwaddr base,
MemoryRegion * mr,
NICInfo * nd,
qemu_irq tx_irq,
qemu_irq rx_irq,
qemu_irq err_irq)
{
DeviceState *dev;
dev = qdev_new("eTSEC");
qdev_set_nic_properties(dev, nd);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, tx_irq);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, rx_irq);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, err_irq);
memory_region_add_subregion(mr, base,
SYS_BUS_DEVICE(dev)->mmio[0].memory);
return dev;
}

7
hw/net/fsl_etsec/etsec.h
View File

@ -155,13 +155,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(eTSEC, ETSEC_COMMON)
#define eTSEC_TRANSMIT 1
#define eTSEC_RECEIVE 2
DeviceState *etsec_create(hwaddr base,
MemoryRegion *mr,
NICInfo *nd,
qemu_irq tx_irq,
qemu_irq rx_irq,
qemu_irq err_irq);
void etsec_update_irq(eTSEC *etsec);
void etsec_walk_tx_ring(eTSEC *etsec, int ring_nbr);

9
hw/rtc/mc146818rtc.c
View File

@ -74,6 +74,8 @@
#define RTC_CLOCK_RATE 32768
#define UIP_HOLD_LENGTH (8 * NANOSECONDS_PER_SECOND / 32768)
#define RTC_ISA_BASE 0x70
static void rtc_set_time(RTCState *s);
static void rtc_update_time(RTCState *s);
static void rtc_set_cmos(RTCState *s, const struct tm *tm);
@ -941,7 +943,7 @@ static void rtc_realizefn(DeviceState *dev, Error **errp)
qemu_register_suspend_notifier(&s->suspend_notifier);
memory_region_init_io(&s->io, OBJECT(s), &cmos_ops, s, "rtc", 2);
isa_register_ioport(isadev, &s->io, RTC_ISA_BASE);
isa_register_ioport(isadev, &s->io, s->io_base);
/* register rtc 0x70 port for coalesced_pio */
memory_region_set_flush_coalesced(&s->io);
@ -950,7 +952,7 @@ static void rtc_realizefn(DeviceState *dev, Error **errp)
memory_region_add_subregion(&s->io, 0, &s->coalesced_io);
memory_region_add_coalescing(&s->coalesced_io, 0, 1);
qdev_set_legacy_instance_id(dev, RTC_ISA_BASE, 3);
qdev_set_legacy_instance_id(dev, s->io_base, 3);
object_property_add_tm(OBJECT(s), "date", rtc_get_date);
@ -983,6 +985,7 @@ ISADevice *mc146818_rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
static Property mc146818rtc_properties[] = {
DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
DEFINE_PROP_UINT16("iobase", RTCState, io_base, RTC_ISA_BASE),
DEFINE_PROP_UINT8("irq", RTCState, isairq, RTC_ISA_IRQ),
DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", RTCState,
lost_tick_policy, LOST_TICK_POLICY_DISCARD),
@ -1028,7 +1031,7 @@ static void rtc_build_aml(AcpiDevAmlIf *adev, Aml *scope)
* does, even though qemu only responds to the first two ports.
*/
crs = aml_resource_template();
aml_append(crs, aml_io(AML_DECODE16, RTC_ISA_BASE, RTC_ISA_BASE,
aml_append(crs, aml_io(AML_DECODE16, s->io_base, s->io_base,
0x01, 0x08));
aml_append(crs, aml_irq_no_flags(s->isairq));

2
hw/sparc64/sun4u.c
View File

@ -334,7 +334,7 @@ static void ebus_realize(PCIDevice *pci_dev, Error **errp)
parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS);
/* Keyboard */
isa_create_simple(s->isa_bus, "i8042");
isa_create_simple(s->isa_bus, TYPE_I8042);
/* Floppy */
for (i = 0; i < MAX_FD; i++) {

3
include/exec/cpu-all.h
View File

@ -419,11 +419,8 @@ static inline bool tlb_hit(target_ulong tlb_addr, target_ulong addr)
}
#ifdef CONFIG_TCG
/* accel/tcg/cpu-exec.c */
void dump_drift_info(GString *buf);
/* accel/tcg/translate-all.c */
void dump_exec_info(GString *buf);
void dump_opcount_info(GString *buf);
#endif /* CONFIG_TCG */
#endif /* !CONFIG_USER_ONLY */

75
include/hw/acpi/piix4.h Normal file
View File

@ -0,0 +1,75 @@
/*
* ACPI implementation
*
* Copyright (c) 2006 Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License version 2.1 as published by the Free Software Foundation.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>
*
* Contributions after 2012-01-13 are licensed under the terms of the
* GNU GPL, version 2 or (at your option) any later version.
*/
#ifndef HW_ACPI_PIIX4_H
#define HW_ACPI_PIIX4_H
#include "hw/pci/pci.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/cpu_hotplug.h"
#include "hw/acpi/memory_hotplug.h"
#include "hw/acpi/pcihp.h"
#include "hw/i2c/pm_smbus.h"
#include "hw/isa/apm.h"
#define TYPE_PIIX4_PM "PIIX4_PM"
OBJECT_DECLARE_SIMPLE_TYPE(PIIX4PMState, PIIX4_PM)
struct PIIX4PMState {
/*< private >*/
PCIDevice parent_obj;
/*< public >*/
MemoryRegion io;
uint32_t io_base;
MemoryRegion io_gpe;
ACPIREGS ar;
APMState apm;
PMSMBus smb;
uint32_t smb_io_base;
qemu_irq irq;
qemu_irq smi_irq;
bool smm_enabled;
bool smm_compat;
Notifier machine_ready;
Notifier powerdown_notifier;
AcpiPciHpState acpi_pci_hotplug;
bool use_acpi_hotplug_bridge;
bool use_acpi_root_pci_hotplug;
bool not_migrate_acpi_index;
uint8_t disable_s3;
uint8_t disable_s4;
uint8_t s4_val;
bool cpu_hotplug_legacy;
AcpiCpuHotplug gpe_cpu;
CPUHotplugState cpuhp_state;
MemHotplugState acpi_memory_hotplug;
};
#endif

3
include/hw/block/fdc.h
View File

@ -10,8 +10,7 @@
#define TYPE_ISA_FDC "isa-fdc"
void isa_fdc_init_drives(ISADevice *fdc, DriveInfo **fds);
void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
hwaddr mmio_base, DriveInfo **fds);
void fdctrl_init_sysbus(qemu_irq irq, hwaddr mmio_base, DriveInfo **fds);
void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
DriveInfo **fds, qemu_irq *fdc_tc);

14
include/hw/i386/pc.h
View File

@ -167,19 +167,13 @@ void pc_basic_device_init(struct PCMachineState *pcms,
ISADevice **rtc_state,
bool create_fdctrl,
uint32_t hpet_irqs);
void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
void pc_cmos_init(PCMachineState *pcms,
BusState *ide0, BusState *ide1,
ISADevice *s);
void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus);
void pc_pci_device_init(PCIBus *pci_bus);
typedef void (*cpu_set_smm_t)(int smm, void *arg);
void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs);
ISADevice *pc_find_fdc0(void);
/* port92.c */
#define PORT92_A20_LINE "a20"
@ -288,14 +282,6 @@ extern const size_t pc_compat_1_5_len;
extern GlobalProperty pc_compat_1_4[];
extern const size_t pc_compat_1_4_len;
/* Helper for setting model-id for CPU models that changed model-id
* depending on QEMU versions up to QEMU 2.4.
*/
#define PC_CPU_MODEL_IDS(v) \
{ "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
{ "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
{ "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
#define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \
static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \
{ \

2
include/hw/isa/isa.h
View File

@ -129,6 +129,4 @@ static inline ISABus *isa_bus_from_device(ISADevice *d)
return ISA_BUS(qdev_get_parent_bus(DEVICE(d)));
}
#define TYPE_PIIX4_PCI_DEVICE "piix4-isa"
#endif

2
include/hw/rtc/mc146818rtc.h
View File

@ -26,6 +26,7 @@ struct RTCState {
uint8_t cmos_data[128];
uint8_t cmos_index;
uint8_t isairq;
uint16_t io_base;
int32_t base_year;
uint64_t base_rtc;
uint64_t last_update;
@ -49,7 +50,6 @@ struct RTCState {
};
#define RTC_ISA_IRQ 8
#define RTC_ISA_BASE 0x70
ISADevice *mc146818_rtc_init(ISABus *bus, int base_year,
qemu_irq intercept_irq);

12
include/hw/southbridge/piix.h
View File

@ -15,12 +15,6 @@
#include "hw/pci/pci.h"
#include "qom/object.h"
#define TYPE_PIIX4_PM "PIIX4_PM"
I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
qemu_irq sci_irq, qemu_irq smi_irq,
int smm_enabled, DeviceState **piix4_pm);
/* PIRQRC[A:D]: PIRQx Route Control Registers */
#define PIIX_PIRQCA 0x60
#define PIIX_PIRQCB 0x61
@ -70,8 +64,8 @@ typedef struct PIIXState PIIX3State;
DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE,
TYPE_PIIX3_PCI_DEVICE)
PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus);
DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus);
#define TYPE_PIIX3_DEVICE "PIIX3"
#define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen"
#define TYPE_PIIX4_PCI_DEVICE "piix4-isa"
#endif

2
target/mips/cpu.c
View File

@ -305,7 +305,7 @@ static void mips_cpu_reset(DeviceState *dev)
for (i = 0; i < 7; i++) {
env->CP0_WatchLo[i] = 0;
env->CP0_WatchHi[i] = 0x80000000;
env->CP0_WatchHi[i] = 1 << CP0WH_M;
}
env->CP0_WatchLo[7] = 0;
env->CP0_WatchHi[7] = 0;

3
target/mips/cpu.h
View File

@ -1005,6 +1005,7 @@ typedef struct CPUArchState {
*/
uint64_t CP0_WatchHi[8];
#define CP0WH_ASID 16
#define CP0WH_M 31
/*
* CP0 Register 20
*/
@ -1076,7 +1077,7 @@ typedef struct CPUArchState {
#define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
uint32_t hflags; /* CPU State */
/* TMASK defines different execution modes */
#define MIPS_HFLAG_TMASK 0x1F5807FF
#define MIPS_HFLAG_TMASK 0x3F5807FF
#define MIPS_HFLAG_MODE 0x00007 /* execution modes */
/*
* The KSU flags must be the lowest bits in hflags. The flag order

2
target/mips/tcg/msa_helper.c
View File

@ -8329,7 +8329,7 @@ void helper_msa_st_b(CPUMIPSState *env, uint32_t wd,
/* Store 8 bytes at a time. Vector element ordering makes this LE. */
cpu_stq_le_data_ra(env, addr + 0, pwd->d[0], ra);
cpu_stq_le_data_ra(env, addr + 0, pwd->d[1], ra);
cpu_stq_le_data_ra(env, addr + 8, pwd->d[1], ra);
}
void helper_msa_st_h(CPUMIPSState *env, uint32_t wd,

29
target/mips/tcg/msa_translate.c
View File

@ -68,8 +68,8 @@ struct dfe {
static int df_extract_val(DisasContext *ctx, int x, const struct dfe *s)
{
for (unsigned i = 0; i < 4; i++) {
if (extract32(x, s->start, s->length) == s->mask) {
return extract32(x, 0, s->start);
if (extract32(x, s[i].start, s[i].length) == s[i].mask) {
return extract32(x, 0, s[i].start);
}
}
return -1;
@ -82,7 +82,7 @@ static int df_extract_val(DisasContext *ctx, int x, const struct dfe *s)
static int df_extract_df(DisasContext *ctx, int x, const struct dfe *s)
{
for (unsigned i = 0; i < 4; i++) {
if (extract32(x, s->start, s->length) == s->mask) {
if (extract32(x, s[i].start, s[i].length) == s[i].mask) {
return i;
}
}
@ -399,7 +399,7 @@ TRANS(BSETI, trans_msa_bit, gen_helper_msa_bseti_df);
TRANS(BNEGI, trans_msa_bit, gen_helper_msa_bnegi_df);
TRANS(BINSLI, trans_msa_bit, gen_helper_msa_binsli_df);
TRANS(BINSRI, trans_msa_bit, gen_helper_msa_binsri_df);
TRANS(SAT_S, trans_msa_bit, gen_helper_msa_sat_u_df);
TRANS(SAT_S, trans_msa_bit, gen_helper_msa_sat_s_df);
TRANS(SAT_U, trans_msa_bit, gen_helper_msa_sat_u_df);
TRANS(SRARI, trans_msa_bit, gen_helper_msa_srari_df);
TRANS(SRLRI, trans_msa_bit, gen_helper_msa_srlri_df);
@ -599,12 +599,7 @@ static bool trans_msa_elm_fn(DisasContext *ctx, arg_msa_elm_df *a,
return false;
}
if (check_msa_enabled(ctx)) {
return true;
}
if (a->wd == 0) {
/* Treat as NOP. */
if (!check_msa_enabled(ctx)) {
return true;
}
@ -624,6 +619,11 @@ static bool trans_msa_elm_fn(DisasContext *ctx, arg_msa_elm_df *a,
static bool trans_COPY_U(DisasContext *ctx, arg_msa_elm_df *a)
{
if (a->wd == 0) {
/* Treat as NOP. */
return true;
}
static gen_helper_piii * const gen_msa_copy_u[4] = {
gen_helper_msa_copy_u_b, gen_helper_msa_copy_u_h,
NULL_IF_MIPS32(gen_helper_msa_copy_u_w), NULL
@ -634,6 +634,11 @@ static bool trans_COPY_U(DisasContext *ctx, arg_msa_elm_df *a)
static bool trans_COPY_S(DisasContext *ctx, arg_msa_elm_df *a)
{
if (a->wd == 0) {
/* Treat as NOP. */
return true;
}
static gen_helper_piii * const gen_msa_copy_s[4] = {
gen_helper_msa_copy_s_b, gen_helper_msa_copy_s_h,
gen_helper_msa_copy_s_w, NULL_IF_MIPS32(gen_helper_msa_copy_s_d)
@ -747,8 +752,8 @@ static bool trans_msa_2rf(DisasContext *ctx, arg_msa_r *a,
}
TRANS(FCLASS, trans_msa_2rf, gen_helper_msa_fclass_df);
TRANS(FTRUNC_S, trans_msa_2rf, gen_helper_msa_fclass_df);
TRANS(FTRUNC_U, trans_msa_2rf, gen_helper_msa_ftrunc_s_df);
TRANS(FTRUNC_S, trans_msa_2rf, gen_helper_msa_ftrunc_s_df);
TRANS(FTRUNC_U, trans_msa_2rf, gen_helper_msa_ftrunc_u_df);
TRANS(FSQRT, trans_msa_2rf, gen_helper_msa_fsqrt_df);
TRANS(FRSQRT, trans_msa_2rf, gen_helper_msa_frsqrt_df);
TRANS(FRCP, trans_msa_2rf, gen_helper_msa_frcp_df);

33
target/mips/tcg/nanomips_translate.c.inc
View File

@ -1597,7 +1597,7 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
check_dsp(ctx);
switch (extract32(ctx->opcode, 12, 2)) {
case NM_MTHLIP:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t0, v2 >> 3);
gen_helper_mthlip(t0, v0_t, cpu_env);
break;
case NM_SHILOV:
@ -2036,7 +2036,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
case NM_EXTRV_S_H:
check_dsp(ctx);
tcg_gen_movi_tl(t0, rd >> 3);
gen_helper_extr_s_h(t0, t0, v0_t, cpu_env);
gen_helper_extr_s_h(t0, t0, v1_t, cpu_env);
gen_store_gpr(t0, ret);
break;
}
@ -2707,6 +2707,9 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
case NM_SDC1XS:
tcg_gen_shli_tl(t0, t0, 3);
break;
default:
gen_reserved_instruction(ctx);
goto out;
}
}
gen_op_addr_add(ctx, t0, t0, t1);
@ -2797,6 +2800,7 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
break;
}
out:
tcg_temp_free(t0);
tcg_temp_free(t1);
}
@ -3944,6 +3948,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_shift_imm(ctx, OPC_ROTR, rt, rs,
extract32(ctx->opcode, 0, 5));
break;
default:
gen_reserved_instruction(ctx);
break;
}
}
break;
@ -4245,6 +4252,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
check_xnp(ctx);
gen_llwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
break;
default:
gen_reserved_instruction(ctx);
break;
}
break;
case NM_P_SC:
@ -4257,6 +4267,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5),
false);
break;
default:
gen_reserved_instruction(ctx);
break;
}
break;
case NM_CACHE:
@ -4265,6 +4278,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_cache_operation(ctx, rt, rs, s);
}
break;
default:
gen_reserved_instruction(ctx);
break;
}
break;
case NM_P_LS_E0:
@ -4371,6 +4387,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
default:
gen_reserved_instruction(ctx);
break;
}
break;
case NM_P_LS_WM:
@ -4478,12 +4497,13 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
case NM_P_BR3A:
s = sextract32(ctx->opcode, 0, 1) << 14 |
extract32(ctx->opcode, 1, 13) << 1;
check_cp1_enabled(ctx);
switch (extract32(ctx->opcode, 16, 5)) {
case NM_BC1EQZC:
check_cp1_enabled(ctx);
gen_compute_branch_cp1_nm(ctx, OPC_BC1EQZ, rt, s);
break;
case NM_BC1NEZC:
check_cp1_enabled(ctx);
gen_compute_branch_cp1_nm(ctx, OPC_BC1NEZ, rt, s);
break;
case NM_BPOSGE32C:
@ -4527,7 +4547,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
switch (extract32(ctx->opcode, 14, 2)) {
case NM_BNEC:
check_nms(ctx);
gen_compute_branch_nm(ctx, OPC_BNE, 4, rs, rt, s);
if (rs == rt) {
/* NOP */
ctx->hflags |= MIPS_HFLAG_FBNSLOT;
} else {
gen_compute_branch_nm(ctx, OPC_BNE, 4, rs, rt, s);
}
break;
case NM_BLTC:
if (rs != 0 && rt != 0 && rs == rt) {

3
target/mips/tcg/sysemu/cp0_helper.c
View File

@ -1396,10 +1396,11 @@ void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
{
uint64_t mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID);
uint64_t m_bit = env->CP0_WatchHi[sel] & (1 << CP0WH_M); /* read-only */
if ((env->CP0_Config5 >> CP0C5_MI) & 1) {
mask |= 0xFFFFFFFF00000000ULL; /* MMID */
}
env->CP0_WatchHi[sel] = arg1 & mask;
env->CP0_WatchHi[sel] = m_bit | (arg1 & mask);
env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
}

5
target/mips/tcg/translate.c
View File

@ -16023,8 +16023,9 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
#else
ctx->mem_idx = hflags_mmu_index(ctx->hflags);
#endif
ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS_R6 |
INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN;
ctx->default_tcg_memop_mask = (!(ctx->insn_flags & ISA_NANOMIPS32) &&
(ctx->insn_flags & (ISA_MIPS_R6 |
INSN_LOONGSON3A))) ? MO_UNALN : MO_ALIGN;
/*
* Execute a branch and its delay slot as a single instruction.