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target-arm: A64: Move handle_2misc_narrow function
Move the handle_2misc_narrow() function up the file so that it can be called from disas_simd_scalar_two_reg_misc(). Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-22-git-send-email-peter.maydell@linaro.org
This commit is contained in:
Alex Bennée
Peter Maydell
parent
b6d4443a7b
commit
8b092ca9ef
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@ -7200,6 +7200,96 @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode,
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tcg_temp_free_ptr(fpst);
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}
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static void handle_2misc_narrow(DisasContext *s, int opcode, bool u, bool is_q,
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int size, int rn, int rd)
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{
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/* Handle 2-reg-misc ops which are narrowing (so each 2*size element
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* in the source becomes a size element in the destination).
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*/
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int pass;
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TCGv_i32 tcg_res[2];
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int destelt = is_q ? 2 : 0;
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for (pass = 0; pass < 2; pass++) {
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TCGv_i64 tcg_op = tcg_temp_new_i64();
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NeonGenNarrowFn *genfn = NULL;
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NeonGenNarrowEnvFn *genenvfn = NULL;
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read_vec_element(s, tcg_op, rn, pass, MO_64);
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tcg_res[pass] = tcg_temp_new_i32();
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switch (opcode) {
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case 0x12: /* XTN, SQXTUN */
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{
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static NeonGenNarrowFn * const xtnfns[3] = {
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gen_helper_neon_narrow_u8,
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gen_helper_neon_narrow_u16,
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tcg_gen_trunc_i64_i32,
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};
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static NeonGenNarrowEnvFn * const sqxtunfns[3] = {
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gen_helper_neon_unarrow_sat8,
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gen_helper_neon_unarrow_sat16,
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gen_helper_neon_unarrow_sat32,
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};
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if (u) {
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genenvfn = sqxtunfns[size];
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} else {
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genfn = xtnfns[size];
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}
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break;
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}
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case 0x14: /* SQXTN, UQXTN */
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{
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static NeonGenNarrowEnvFn * const fns[3][2] = {
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{ gen_helper_neon_narrow_sat_s8,
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gen_helper_neon_narrow_sat_u8 },
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{ gen_helper_neon_narrow_sat_s16,
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gen_helper_neon_narrow_sat_u16 },
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{ gen_helper_neon_narrow_sat_s32,
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gen_helper_neon_narrow_sat_u32 },
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};
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genenvfn = fns[size][u];
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break;
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}
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case 0x16: /* FCVTN, FCVTN2 */
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/* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
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if (size == 2) {
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gen_helper_vfp_fcvtsd(tcg_res[pass], tcg_op, cpu_env);
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} else {
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TCGv_i32 tcg_lo = tcg_temp_new_i32();
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TCGv_i32 tcg_hi = tcg_temp_new_i32();
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tcg_gen_trunc_i64_i32(tcg_lo, tcg_op);
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gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, cpu_env);
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tcg_gen_shri_i64(tcg_op, tcg_op, 32);
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tcg_gen_trunc_i64_i32(tcg_hi, tcg_op);
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gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, cpu_env);
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tcg_gen_deposit_i32(tcg_res[pass], tcg_lo, tcg_hi, 16, 16);
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tcg_temp_free_i32(tcg_lo);
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tcg_temp_free_i32(tcg_hi);
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}
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break;
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default:
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g_assert_not_reached();
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}
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if (genfn) {
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genfn(tcg_res[pass], tcg_op);
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} else if (genenvfn) {
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genenvfn(tcg_res[pass], cpu_env, tcg_op);
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}
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tcg_temp_free_i64(tcg_op);
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}
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for (pass = 0; pass < 2; pass++) {
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write_vec_element_i32(s, tcg_res[pass], rd, destelt + pass, MO_32);
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tcg_temp_free_i32(tcg_res[pass]);
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}
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if (!is_q) {
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clear_vec_high(s, rd);
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}
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}
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/* C3.6.12 AdvSIMD scalar two reg misc
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* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
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* +-----+---+-----------+------+-----------+--------+-----+------+------+
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@ -8745,96 +8835,6 @@ static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn)
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}
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}
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static void handle_2misc_narrow(DisasContext *s, int opcode, bool u, bool is_q,
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int size, int rn, int rd)
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{
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/* Handle 2-reg-misc ops which are narrowing (so each 2*size element
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* in the source becomes a size element in the destination).
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*/
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int pass;
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TCGv_i32 tcg_res[2];
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int destelt = is_q ? 2 : 0;
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for (pass = 0; pass < 2; pass++) {
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TCGv_i64 tcg_op = tcg_temp_new_i64();
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NeonGenNarrowFn *genfn = NULL;
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NeonGenNarrowEnvFn *genenvfn = NULL;
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read_vec_element(s, tcg_op, rn, pass, MO_64);
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tcg_res[pass] = tcg_temp_new_i32();
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switch (opcode) {
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case 0x12: /* XTN, SQXTUN */
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{
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static NeonGenNarrowFn * const xtnfns[3] = {
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gen_helper_neon_narrow_u8,
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gen_helper_neon_narrow_u16,
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tcg_gen_trunc_i64_i32,
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};
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static NeonGenNarrowEnvFn * const sqxtunfns[3] = {
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gen_helper_neon_unarrow_sat8,
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gen_helper_neon_unarrow_sat16,
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gen_helper_neon_unarrow_sat32,
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};
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if (u) {
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genenvfn = sqxtunfns[size];
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} else {
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genfn = xtnfns[size];
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}
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break;
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}
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case 0x14: /* SQXTN, UQXTN */
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{
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static NeonGenNarrowEnvFn * const fns[3][2] = {
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{ gen_helper_neon_narrow_sat_s8,
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gen_helper_neon_narrow_sat_u8 },
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{ gen_helper_neon_narrow_sat_s16,
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gen_helper_neon_narrow_sat_u16 },
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{ gen_helper_neon_narrow_sat_s32,
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gen_helper_neon_narrow_sat_u32 },
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};
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genenvfn = fns[size][u];
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break;
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}
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case 0x16: /* FCVTN, FCVTN2 */
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/* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
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if (size == 2) {
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gen_helper_vfp_fcvtsd(tcg_res[pass], tcg_op, cpu_env);
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} else {
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TCGv_i32 tcg_lo = tcg_temp_new_i32();
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TCGv_i32 tcg_hi = tcg_temp_new_i32();
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tcg_gen_trunc_i64_i32(tcg_lo, tcg_op);
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gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, cpu_env);
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tcg_gen_shri_i64(tcg_op, tcg_op, 32);
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tcg_gen_trunc_i64_i32(tcg_hi, tcg_op);
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gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, cpu_env);
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tcg_gen_deposit_i32(tcg_res[pass], tcg_lo, tcg_hi, 16, 16);
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tcg_temp_free_i32(tcg_lo);
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tcg_temp_free_i32(tcg_hi);
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}
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break;
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default:
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g_assert_not_reached();
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}
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if (genfn) {
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genfn(tcg_res[pass], tcg_op);
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} else if (genenvfn) {
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genenvfn(tcg_res[pass], cpu_env, tcg_op);
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}
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tcg_temp_free_i64(tcg_op);
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}
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for (pass = 0; pass < 2; pass++) {
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write_vec_element_i32(s, tcg_res[pass], rd, destelt + pass, MO_32);
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tcg_temp_free_i32(tcg_res[pass]);
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}
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if (!is_q) {
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clear_vec_high(s, rd);
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}
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}
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static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,
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int size, int rn, int rd)
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{
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