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hw/pci-host: Use register definitions from PCI standard 

No need to document magic values when the definition names
from "standard-headers/linux/pci_regs.h" are self-explicit.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230105173702.56610-1-philmd@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
This commit is contained in:
Philippe Mathieu-Daudé 2023-01-05 18:37:02 +01:00 committed by Michael S. Tsirkin
parent 744734ccc9
commit 8a8c9c3a74
3 changed files with 15 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hw/pci-host/grackle.c
View File

@ -91,7 +91,7 @@ static void grackle_init(Object *obj)
static void grackle_pci_realize(PCIDevice *d, Error **errp) static void grackle_pci_realize(PCIDevice *d, Error **errp)
{ {
d->config[0x09] = 0x01; d->config[PCI_CLASS_PROG] = 0x01;
} }
static void grackle_pci_class_init(ObjectClass *klass, void *data) static void grackle_pci_class_init(ObjectClass *klass, void *data)

6
hw/pci-host/raven.c
View File

@ -330,9 +330,9 @@ static void raven_realize(PCIDevice *d, Error **errp)
char *filename; char *filename;
int bios_size = -1; int bios_size = -1;
d->config[0x0C] = 0x08; // cache_line_size d->config[PCI_CACHE_LINE_SIZE] = 0x08;
d->config[0x0D] = 0x10; // latency_timer d->config[PCI_LATENCY_TIMER] = 0x10;
d->config[0x34] = 0x00; // capabilities_pointer d->config[PCI_CAPABILITY_LIST] = 0x00;
memory_region_init_rom_nomigrate(&s->bios, OBJECT(s), "bios", BIOS_SIZE, memory_region_init_rom_nomigrate(&s->bios, OBJECT(s), "bios", BIOS_SIZE,
&error_fatal); &error_fatal);

33
hw/pci-host/uninorth.c
View File

@ -276,12 +276,9 @@ static void pci_unin_internal_init(Object *obj)
static void unin_main_pci_host_realize(PCIDevice *d, Error **errp) static void unin_main_pci_host_realize(PCIDevice *d, Error **errp)
{ {
/* cache_line_size */ d->config[PCI_CACHE_LINE_SIZE] = 0x08;
d->config[0x0C] = 0x08; d->config[PCI_LATENCY_TIMER] = 0x10;
/* latency_timer */ d->config[PCI_CAPABILITY_LIST] = 0x00;
d->config[0x0D] = 0x10;
/* capabilities_pointer */
d->config[0x34] = 0x00;
/* /*
* Set kMacRISCPCIAddressSelect (0x48) register to indicate PCI * Set kMacRISCPCIAddressSelect (0x48) register to indicate PCI
@ -296,30 +293,22 @@ static void unin_main_pci_host_realize(PCIDevice *d, Error **errp)
static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp) static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp)
{ {
/* cache_line_size */ d->config[PCI_CACHE_LINE_SIZE] = 0x08;
d->config[0x0C] = 0x08; d->config[PCI_LATENCY_TIMER] = 0x10;
/* latency_timer */ /* d->config[PCI_CAPABILITY_LIST] = 0x80; */
d->config[0x0D] = 0x10;
/* capabilities_pointer
d->config[0x34] = 0x80; */
} }
static void u3_agp_pci_host_realize(PCIDevice *d, Error **errp) static void u3_agp_pci_host_realize(PCIDevice *d, Error **errp)
{ {
/* cache line size */ d->config[PCI_CACHE_LINE_SIZE] = 0x08;
d->config[0x0C] = 0x08; d->config[PCI_LATENCY_TIMER] = 0x10;
/* latency timer */
d->config[0x0D] = 0x10;
} }
static void unin_internal_pci_host_realize(PCIDevice *d, Error **errp) static void unin_internal_pci_host_realize(PCIDevice *d, Error **errp)
{ {
/* cache_line_size */ d->config[PCI_CACHE_LINE_SIZE] = 0x08;
d->config[0x0C] = 0x08; d->config[PCI_LATENCY_TIMER] = 0x10;
/* latency_timer */ d->config[PCI_CAPABILITY_LIST] = 0x00;
d->config[0x0D] = 0x10;
/* capabilities_pointer */
d->config[0x34] = 0x00;
} }
static void unin_main_pci_host_class_init(ObjectClass *klass, void *data) static void unin_main_pci_host_class_init(ObjectClass *klass, void *data)