mirror of https://github.com/xemu-project/xemu.git
target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}
Co-authored-by: ardxwe <ardxwe@gmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220211043920.28981-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -587,6 +587,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
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cpu->cfg.ext_d = true;
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}
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if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
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cpu->cfg.ext_zhinxmin) {
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cpu->cfg.ext_zfinx = true;
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}
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/* Set the ISA extensions, checks should have happened above */
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if (cpu->cfg.ext_i) {
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ext |= RVI;
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@ -665,6 +670,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
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if (cpu->cfg.ext_j) {
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ext |= RVJ;
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}
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if (cpu->cfg.ext_zfinx && ((ext & (RVF | RVD)) || cpu->cfg.ext_zfh ||
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cpu->cfg.ext_zfhmin)) {
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error_setg(errp,
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"'Zfinx' cannot be supported together with 'F', 'D', 'Zfh',"
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" 'Zfhmin'");
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return;
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}
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set_misa(env, env->misa_mxl, ext);
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}
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@ -362,8 +362,12 @@ struct RISCVCPUConfig {
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bool ext_svinval;
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bool ext_svnapot;
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bool ext_svpbmt;
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bool ext_zdinx;
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bool ext_zfh;
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bool ext_zfhmin;
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bool ext_zfinx;
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bool ext_zhinx;
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bool ext_zhinxmin;
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bool ext_zve32f;
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bool ext_zve64f;
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