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target/ppc: Fix instruction loading endianness in alignment interrupt 

powerpc ifetch endianness depends on MSR[LE] so it has to byteswap
after cpu_ldl_code(). This corrects DSISR bits in alignment
interrupts when running in little endian mode.

Reviewed-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Nicholas Piggin 2023-06-20 23:10:41 +10:00 committed by Cédric Le Goater
parent 6b8a05373b
commit 888050cf51
1 changed files with 21 additions and 1 deletions
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22
target/ppc/excp_helper.c
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@ -133,6 +133,26 @@ static void dump_hcall(CPUPPCState *env)
env->nip); env->nip);
} }
#ifdef CONFIG_TCG
/* Return true iff byteswap is needed to load instruction */
static inline bool insn_need_byteswap(CPUArchState *env)
{
/* SYSTEM builds TARGET_BIG_ENDIAN. Need to swap when MSR[LE] is set */
return !!(env->msr & ((target_ulong)1 << MSR_LE));
}
static uint32_t ppc_ldl_code(CPUArchState *env, hwaddr addr)
{
uint32_t insn = cpu_ldl_code(env, addr);
if (insn_need_byteswap(env)) {
insn = bswap32(insn);
}
return insn;
}
#endif
static void ppc_excp_debug_sw_tlb(CPUPPCState *env, int excp) static void ppc_excp_debug_sw_tlb(CPUPPCState *env, int excp)
{ {
const char *es; const char *es;
@ -3104,7 +3124,7 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
/* Restore state and reload the insn we executed, for filling in DSISR. */ /* Restore state and reload the insn we executed, for filling in DSISR. */
cpu_restore_state(cs, retaddr); cpu_restore_state(cs, retaddr);
insn = cpu_ldl_code(env, env->nip); insn = ppc_ldl_code(env, env->nip);
switch (env->mmu_model) { switch (env->mmu_model) {
case POWERPC_MMU_SOFT_4xx: case POWERPC_MMU_SOFT_4xx: