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target/arm: Decode FP instructions for M profile 

Correct the decode of the M-profile "coprocessor and
floating-point instructions" space:
 * op0 == 0b11 is always unallocated
 * if the CPU has an FPU then all insns with op1 == 0b101
   are floating point and go to disas_vfp_insn()

For the moment we leave VLLDM and VLSTM as NOPs; in
a later commit we will fill in the proper implementation
for the case where an FPU is present.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190416125744.27770-7-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2019-04-29 17:35:59 +01:00
parent d87513c0ab
commit 8859ba3c96
1 changed files with 22 additions and 4 deletions
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26
target/arm/translate.c
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@ -11728,10 +11728,19 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
case 6: case 7: case 14: case 15:
/* Coprocessor. */
if (arm_dc_feature(s, ARM_FEATURE_M)) {
/* We don't currently implement M profile FP support,
* so this entire space should give a NOCP fault, with
* the exception of the v8M VLLDM and VLSTM insns, which
* must be NOPs in Secure state and UNDEF in Nonsecure state.
/* 0b111x_11xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx */
if (extract32(insn, 24, 2) == 3) {
goto illegal_op; /* op0 = 0b11 : unallocated */
}
/*
* Decode VLLDM and VLSTM first: these are nonstandard because:
* * if there is no FPU then these insns must NOP in
* Secure state and UNDEF in Nonsecure state
* * if there is an FPU then these insns do not have
* the usual behaviour that disas_vfp_insn() provides of
* being controlled by CPACR/NSACR enable bits or the
* lazy-stacking logic.
*/
if (arm_dc_feature(s, ARM_FEATURE_V8) &&
(insn & 0xffa00f00) == 0xec200a00) {
@ -11745,6 +11754,15 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
/* Just NOP since FP support is not implemented */
break;
}
if (arm_dc_feature(s, ARM_FEATURE_VFP) &&
((insn >> 8) & 0xe) == 10) {
/* FP, and the CPU supports it */
if (disas_vfp_insn(s, insn)) {
goto illegal_op;
}
break;
}
/* All other insns: NOCP */
gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(),
default_exception_el(s));