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target/riscv: Implement SGEIP bit in hip and hie CSRs 

A hypervisor can optionally take guest external interrupts using
SGEIP bit of hip and hie CSRs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-3-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Anup Patel 2022-02-04 23:16:38 +05:30 committed by Alistair Francis
parent dceecac8a2
commit 881df35d3d
3 changed files with 16 additions and 8 deletions
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3
target/riscv/cpu.c
View File

@ -434,6 +434,7 @@ static void riscv_cpu_reset(DeviceState *dev)
} }
} }
env->mcause = 0; env->mcause = 0;
env->miclaim = MIP_SGEIP;
env->pc = env->resetvec; env->pc = env->resetvec;
env->two_stage_lookup = false; env->two_stage_lookup = false;
/* mmte is supposed to have pm.current hardwired to 1 */ /* mmte is supposed to have pm.current hardwired to 1 */
@ -695,7 +696,7 @@ static void riscv_cpu_init(Object *obj)
cpu_set_cpustate_pointers(cpu); cpu_set_cpustate_pointers(cpu);
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12); qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX);
#endif /* CONFIG_USER_ONLY */ #endif /* CONFIG_USER_ONLY */
} }

3
target/riscv/cpu_bits.h
View File

@ -540,6 +540,8 @@ typedef enum RISCVException {
#define IRQ_S_EXT 9 #define IRQ_S_EXT 9
#define IRQ_VS_EXT 10 #define IRQ_VS_EXT 10
#define IRQ_M_EXT 11 #define IRQ_M_EXT 11
#define IRQ_S_GEXT 12
#define IRQ_LOCAL_MAX 16
/* mip masks */ /* mip masks */
#define MIP_USIP (1 << IRQ_U_SOFT) #define MIP_USIP (1 << IRQ_U_SOFT)
@ -554,6 +556,7 @@ typedef enum RISCVException {
#define MIP_SEIP (1 << IRQ_S_EXT) #define MIP_SEIP (1 << IRQ_S_EXT)
#define MIP_VSEIP (1 << IRQ_VS_EXT) #define MIP_VSEIP (1 << IRQ_VS_EXT)
#define MIP_MEIP (1 << IRQ_M_EXT) #define MIP_MEIP (1 << IRQ_M_EXT)
#define MIP_SGEIP (1 << IRQ_S_GEXT)
/* sip masks */ /* sip masks */
#define SIP_SSIP MIP_SSIP #define SIP_SSIP MIP_SSIP

18
target/riscv/csr.c
View File

@ -461,12 +461,13 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
#define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP)
#define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP)
#define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
#define HS_MODE_INTERRUPTS (MIP_SGEIP | VS_MODE_INTERRUPTS)
static const target_ulong delegable_ints = S_MODE_INTERRUPTS | static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
VS_MODE_INTERRUPTS; VS_MODE_INTERRUPTS;
static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS; static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
VS_MODE_INTERRUPTS; HS_MODE_INTERRUPTS;
#define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
(1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
(1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
@ -748,7 +749,7 @@ static RISCVException write_mideleg(CPURISCVState *env, int csrno,
{ {
env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
if (riscv_has_ext(env, RVH)) { if (riscv_has_ext(env, RVH)) {
env->mideleg |= VS_MODE_INTERRUPTS; env->mideleg |= HS_MODE_INTERRUPTS;
} }
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
} }
@ -764,6 +765,9 @@ static RISCVException write_mie(CPURISCVState *env, int csrno,
target_ulong val) target_ulong val)
{ {
env->mie = (env->mie & ~all_ints) | (val & all_ints); env->mie = (env->mie & ~all_ints) | (val & all_ints);
if (!riscv_has_ext(env, RVH)) {
env->mie &= ~MIP_SGEIP;
}
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
} }
@ -1110,7 +1114,7 @@ static RISCVException rmw_sip(CPURISCVState *env, int csrno,
} }
if (ret_value) { if (ret_value) {
*ret_value &= env->mideleg; *ret_value &= env->mideleg & S_MODE_INTERRUPTS;
} }
return ret; return ret;
} }
@ -1228,7 +1232,7 @@ static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
write_mask & hvip_writable_mask); write_mask & hvip_writable_mask);
if (ret_value) { if (ret_value) {
*ret_value &= hvip_writable_mask; *ret_value &= VS_MODE_INTERRUPTS;
} }
return ret; return ret;
} }
@ -1241,7 +1245,7 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno,
write_mask & hip_writable_mask); write_mask & hip_writable_mask);
if (ret_value) { if (ret_value) {
*ret_value &= hip_writable_mask; *ret_value &= HS_MODE_INTERRUPTS;
} }
return ret; return ret;
} }
@ -1249,14 +1253,14 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno,
static RISCVException read_hie(CPURISCVState *env, int csrno, static RISCVException read_hie(CPURISCVState *env, int csrno,
target_ulong *val) target_ulong *val)
{ {
*val = env->mie & VS_MODE_INTERRUPTS; *val = env->mie & HS_MODE_INTERRUPTS;
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
} }
static RISCVException write_hie(CPURISCVState *env, int csrno, static RISCVException write_hie(CPURISCVState *env, int csrno,
target_ulong val) target_ulong val)
{ {
target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS); target_ulong newval = (env->mie & ~HS_MODE_INTERRUPTS) | (val & HS_MODE_INTERRUPTS);
return write_mie(env, CSR_MIE, newval); return write_mie(env, CSR_MIE, newval);
} }