mirror of https://github.com/xemu-project/xemu.git
linux-headers: Update from v3.14-rc3
Update to tag v3.14-rc3 (6d0abeca3242a88cab8232e4acd7e2bf088f3bc2) Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1392687720-26806-2-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -119,6 +119,26 @@ struct kvm_arch_memory_slot {
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#define KVM_REG_ARM_32_CRN_MASK 0x0000000000007800
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#define KVM_REG_ARM_32_CRN_SHIFT 11
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#define ARM_CP15_REG_SHIFT_MASK(x,n) \
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(((x) << KVM_REG_ARM_ ## n ## _SHIFT) & KVM_REG_ARM_ ## n ## _MASK)
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#define __ARM_CP15_REG(op1,crn,crm,op2) \
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(KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT) | \
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ARM_CP15_REG_SHIFT_MASK(op1, OPC1) | \
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ARM_CP15_REG_SHIFT_MASK(crn, 32_CRN) | \
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ARM_CP15_REG_SHIFT_MASK(crm, CRM) | \
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ARM_CP15_REG_SHIFT_MASK(op2, 32_OPC2))
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#define ARM_CP15_REG32(...) (__ARM_CP15_REG(__VA_ARGS__) | KVM_REG_SIZE_U32)
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#define __ARM_CP15_REG64(op1,crm) \
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(__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64)
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#define ARM_CP15_REG64(...) __ARM_CP15_REG64(__VA_ARGS__)
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#define KVM_REG_ARM_TIMER_CTL ARM_CP15_REG32(0, 14, 3, 1)
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#define KVM_REG_ARM_TIMER_CNT ARM_CP15_REG64(1, 14)
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#define KVM_REG_ARM_TIMER_CVAL ARM_CP15_REG64(3, 14)
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/* Normal registers are mapped as coprocessor 16. */
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#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
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#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / 4)
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@ -143,6 +163,14 @@ struct kvm_arch_memory_slot {
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#define KVM_REG_ARM_VFP_FPINST 0x1009
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#define KVM_REG_ARM_VFP_FPINST2 0x100A
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/* Device Control API: ARM VGIC */
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#define KVM_DEV_ARM_VGIC_GRP_ADDR 0
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#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1
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#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
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#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
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#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
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#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
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#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
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/* KVM_IRQ_LINE irq field index values */
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#define KVM_ARM_IRQ_TYPE_SHIFT 24
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@ -55,8 +55,9 @@ struct kvm_regs {
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#define KVM_ARM_TARGET_AEM_V8 0
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#define KVM_ARM_TARGET_FOUNDATION_V8 1
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#define KVM_ARM_TARGET_CORTEX_A57 2
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#define KVM_ARM_TARGET_XGENE_POTENZA 3
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#define KVM_ARM_NUM_TARGETS 3
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#define KVM_ARM_NUM_TARGETS 4
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/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
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#define KVM_ARM_DEVICE_TYPE_SHIFT 0
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@ -129,6 +130,33 @@ struct kvm_arch_memory_slot {
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#define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007
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#define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0
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#define ARM64_SYS_REG_SHIFT_MASK(x,n) \
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(((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \
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KVM_REG_ARM64_SYSREG_ ## n ## _MASK)
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#define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \
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(KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \
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ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \
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ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
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ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
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ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
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ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
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#define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64)
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#define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1)
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#define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2)
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#define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2)
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/* Device Control API: ARM VGIC */
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#define KVM_DEV_ARM_VGIC_GRP_ADDR 0
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#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1
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#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
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#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
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#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
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#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
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#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
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/* KVM_IRQ_LINE irq field index values */
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#define KVM_ARM_IRQ_TYPE_SHIFT 24
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#define KVM_ARM_IRQ_TYPE_MASK 0xff
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@ -545,6 +545,7 @@ struct kvm_get_htab_header {
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#define KVM_REG_PPC_TCSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb1)
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#define KVM_REG_PPC_PID (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb2)
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#define KVM_REG_PPC_ACOP (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb3)
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#define KVM_REG_PPC_WORT (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb4)
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#define KVM_REG_PPC_VRSAVE (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb4)
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#define KVM_REG_PPC_LPCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb5)
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@ -553,6 +554,8 @@ struct kvm_get_htab_header {
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/* Architecture compatibility level */
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#define KVM_REG_PPC_ARCH_COMPAT (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb7)
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#define KVM_REG_PPC_DABRX (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb8)
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/* Transactional Memory checkpointed state:
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* This is all GPRs, all VSX regs and a subset of SPRs
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*/
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@ -28,6 +28,9 @@
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/* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/
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#define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE (1 << 1)
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/* A partition's reference time stamp counter (TSC) page */
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#define HV_X64_MSR_REFERENCE_TSC 0x40000021
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/*
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* There is a single feature flag that signifies the presence of the MSR
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* that can be used to retrieve both the local APIC Timer frequency as
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@ -149,9 +152,6 @@
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/* MSR used to read the per-partition time reference counter */
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#define HV_X64_MSR_TIME_REF_COUNT 0x40000020
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/* A partition's reference time stamp counter (TSC) page */
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#define HV_X64_MSR_REFERENCE_TSC 0x40000021
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/* MSR used to retrieve the TSC frequency */
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#define HV_X64_MSR_TSC_FREQUENCY 0x40000022
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@ -201,6 +201,9 @@
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#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_MASK \
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(~((1ull << HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
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#define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001
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#define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12
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#define HV_PROCESSOR_POWER_STATE_C0 0
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#define HV_PROCESSOR_POWER_STATE_C1 1
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#define HV_PROCESSOR_POWER_STATE_C2 2
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@ -213,4 +216,11 @@
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#define HV_STATUS_INVALID_ALIGNMENT 4
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#define HV_STATUS_INSUFFICIENT_BUFFERS 19
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typedef struct _HV_REFERENCE_TSC_PAGE {
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__u32 tsc_sequence;
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__u32 res1;
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__u64 tsc_scale;
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__s64 tsc_offset;
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} HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE;
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#endif
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@ -854,6 +854,7 @@ struct kvm_device_attr {
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#define KVM_DEV_VFIO_GROUP 1
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#define KVM_DEV_VFIO_GROUP_ADD 1
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#define KVM_DEV_VFIO_GROUP_DEL 2
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#define KVM_DEV_TYPE_ARM_VGIC_V2 5
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/*
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* ioctls for VM fds
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