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target/riscv: Fixup setting GVA 

In preparation for adding support for the illegal instruction address
let's fixup the Hypervisor extension setting GVA logic and improve the
variable names.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211220064916.107241-3-alistair.francis@opensource.wdc.com
This commit is contained in:
Alistair Francis 2021-12-20 16:49:15 +10:00
parent ea7b5d5af6
commit 86d0c45739
1 changed files with 6 additions and 15 deletions
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21
target/riscv/cpu_helper.c
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@ -998,6 +998,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
RISCVCPU *cpu = RISCV_CPU(cs); RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env; CPURISCVState *env = &cpu->env;
bool write_gva = false;
uint64_t s; uint64_t s;
/* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
@ -1006,7 +1007,6 @@ void riscv_cpu_do_interrupt(CPUState *cs)
bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG);
target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
target_ulong deleg = async ? env->mideleg : env->medeleg; target_ulong deleg = async ? env->mideleg : env->medeleg;
bool write_tval = false;
target_ulong tval = 0; target_ulong tval = 0;
target_ulong htval = 0; target_ulong htval = 0;
target_ulong mtval2 = 0; target_ulong mtval2 = 0;
@ -1035,7 +1035,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
case RISCV_EXCP_INST_PAGE_FAULT: case RISCV_EXCP_INST_PAGE_FAULT:
case RISCV_EXCP_LOAD_PAGE_FAULT: case RISCV_EXCP_LOAD_PAGE_FAULT:
case RISCV_EXCP_STORE_PAGE_FAULT: case RISCV_EXCP_STORE_PAGE_FAULT:
write_tval = true; write_gva = true;
tval = env->badaddr; tval = env->badaddr;
break; break;
default: default:
@ -1072,18 +1072,6 @@ void riscv_cpu_do_interrupt(CPUState *cs)
if (riscv_has_ext(env, RVH)) { if (riscv_has_ext(env, RVH)) {
target_ulong hdeleg = async ? env->hideleg : env->hedeleg; target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
if (env->two_stage_lookup && write_tval) {
/*
* If we are writing a guest virtual address to stval, set
* this to 1. If we are trapping to VS we will set this to 0
* later.
*/
env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 1);
} else {
/* For other HS-mode traps, we set this to 0. */
env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0);
}
if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) { if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) {
/* Trap to VS mode */ /* Trap to VS mode */
/* /*
@ -1094,7 +1082,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
cause == IRQ_VS_EXT) { cause == IRQ_VS_EXT) {
cause = cause - 1; cause = cause - 1;
} }
env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0); write_gva = false;
} else if (riscv_cpu_virt_enabled(env)) { } else if (riscv_cpu_virt_enabled(env)) {
/* Trap into HS mode, from virt */ /* Trap into HS mode, from virt */
riscv_cpu_swap_hypervisor_regs(env); riscv_cpu_swap_hypervisor_regs(env);
@ -1103,6 +1091,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
env->hstatus = set_field(env->hstatus, HSTATUS_SPV, env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
riscv_cpu_virt_enabled(env)); riscv_cpu_virt_enabled(env));
htval = env->guest_phys_fault_addr; htval = env->guest_phys_fault_addr;
riscv_cpu_set_virt_enabled(env, 0); riscv_cpu_set_virt_enabled(env, 0);
@ -1110,7 +1099,9 @@ void riscv_cpu_do_interrupt(CPUState *cs)
/* Trap into HS mode */ /* Trap into HS mode */
env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
htval = env->guest_phys_fault_addr; htval = env->guest_phys_fault_addr;
write_gva = false;
} }
env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva);
} }
s = env->mstatus; s = env->mstatus;