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target/mips: Restrict some system specific declarations to sysemu 

Commit 043715d1e0 ("target/mips: Update ITU to utilize SAARI
and SAAR CP0 registers") declared itc_reconfigure() in public
namespace, while it is restricted to system emulation.

Similarly commit 5679479b9a ("target/mips: Move CP0 helpers
to sysemu/cp0.c") restricted cpu_mips_soft_irq() definition to
system emulation, but forgot to restrict its declaration.

To avoid polluting user-mode emulation with these declarations,
restrict them to sysemu. Also restrict the sysemu ITU/ITC/IRQ
fields from CPUMIPSState.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210617174323.2900831-6-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-05-24 14:28:08 +02:00
parent a9eb3b49fb
commit 85ccd962d6
1 changed files with 7 additions and 3 deletions
target/mips
cpu.h

10
target/mips/cpu.h
View File

@ -1152,13 +1152,13 @@ struct CPUMIPSState {
CPUMIPSMVPContext *mvp;
#if !defined(CONFIG_USER_ONLY)
CPUMIPSTLBContext *tlb;
void *irq[8];
struct MIPSITUState *itu;
MemoryRegion *itc_tag; /* ITC Configuration Tags */
#endif
const mips_def_t *cpu_model;
void *irq[8];
QEMUTimer *timer; /* Internal timer */
struct MIPSITUState *itu;
MemoryRegion *itc_tag; /* ITC Configuration Tags */
target_ulong exception_base; /* ExceptionBase input to the core */
uint64_t cp0_count_ns; /* CP0_Count clock period (in nanoseconds) */
};
@ -1316,12 +1316,16 @@ uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr);
bool mips_um_ksegs_enabled(void);
void mips_um_ksegs_enable(void);
#if !defined(CONFIG_USER_ONLY)
/* mips_int.c */
void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
/* mips_itu.c */
void itc_reconfigure(struct MIPSITUState *tag);
#endif /* !CONFIG_USER_ONLY */
/* helper.c */
target_ulong exception_resume_pc(CPUMIPSState *env);