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target/arm: Convert Neon 2-reg-scalar float multiplies to decodetree
Convert the float versions of VMLA, VMLS and VMUL in the Neon 2-reg-scalar group to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- As noted in the comment on the WRAP_FP_FN macro, we could have had a do_2scalar_fp() function, but for 3 insns it seemed simpler to just do the wrapping to get hold of the fpstatus ptr. (These are the only fp insns in the group.) Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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@ -478,9 +478,12 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
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&2scalar vm=%vm_dp vn=%vn_dp vd=%vd_dp
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VMLA_2sc 1111 001 . 1 . .. .... .... 0000 . 1 . 0 .... @2scalar
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VMLA_F_2sc 1111 001 . 1 . .. .... .... 0001 . 1 . 0 .... @2scalar
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VMLS_2sc 1111 001 . 1 . .. .... .... 0100 . 1 . 0 .... @2scalar
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VMLS_F_2sc 1111 001 . 1 . .. .... .... 0101 . 1 . 0 .... @2scalar
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VMUL_2sc 1111 001 . 1 . .. .... .... 1000 . 1 . 0 .... @2scalar
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VMUL_F_2sc 1111 001 . 1 . .. .... .... 1001 . 1 . 0 .... @2scalar
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]
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}
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@ -2481,3 +2481,68 @@ static bool trans_VMLS_2sc(DisasContext *s, arg_2scalar *a)
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return do_2scalar(s, a, opfn[a->size], accfn[a->size]);
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}
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/*
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* Rather than have a float-specific version of do_2scalar just for
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* three insns, we wrap a NeonGenTwoSingleOpFn to turn it into
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* a NeonGenTwoOpFn.
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*/
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#define WRAP_FP_FN(WRAPNAME, FUNC) \
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static void WRAPNAME(TCGv_i32 rd, TCGv_i32 rn, TCGv_i32 rm) \
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{ \
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TCGv_ptr fpstatus = get_fpstatus_ptr(1); \
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FUNC(rd, rn, rm, fpstatus); \
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tcg_temp_free_ptr(fpstatus); \
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}
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WRAP_FP_FN(gen_VMUL_F_mul, gen_helper_vfp_muls)
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WRAP_FP_FN(gen_VMUL_F_add, gen_helper_vfp_adds)
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WRAP_FP_FN(gen_VMUL_F_sub, gen_helper_vfp_subs)
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static bool trans_VMUL_F_2sc(DisasContext *s, arg_2scalar *a)
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{
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static NeonGenTwoOpFn * const opfn[] = {
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NULL,
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NULL, /* TODO: fp16 support */
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gen_VMUL_F_mul,
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NULL,
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};
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return do_2scalar(s, a, opfn[a->size], NULL);
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}
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static bool trans_VMLA_F_2sc(DisasContext *s, arg_2scalar *a)
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{
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static NeonGenTwoOpFn * const opfn[] = {
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NULL,
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NULL, /* TODO: fp16 support */
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gen_VMUL_F_mul,
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NULL,
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};
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static NeonGenTwoOpFn * const accfn[] = {
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NULL,
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NULL, /* TODO: fp16 support */
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gen_VMUL_F_add,
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NULL,
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};
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return do_2scalar(s, a, opfn[a->size], accfn[a->size]);
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}
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static bool trans_VMLS_F_2sc(DisasContext *s, arg_2scalar *a)
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{
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static NeonGenTwoOpFn * const opfn[] = {
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NULL,
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NULL, /* TODO: fp16 support */
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gen_VMUL_F_mul,
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NULL,
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};
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static NeonGenTwoOpFn * const accfn[] = {
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NULL,
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NULL, /* TODO: fp16 support */
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gen_VMUL_F_sub,
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NULL,
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};
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return do_2scalar(s, a, opfn[a->size], accfn[a->size]);
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}
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@ -5187,15 +5187,11 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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case 0: /* Integer VMLA scalar */
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case 4: /* Integer VMLS scalar */
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case 8: /* Integer VMUL scalar */
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return 1; /* handled by decodetree */
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case 1: /* Float VMLA scalar */
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case 5: /* Floating point VMLS scalar */
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case 9: /* Floating point VMUL scalar */
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if (size == 1) {
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return 1;
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}
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/* fall through */
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return 1; /* handled by decodetree */
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case 12: /* VQDMULH scalar */
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case 13: /* VQRDMULH scalar */
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if (u && ((rd | rn) & 1)) {
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@ -5212,41 +5208,14 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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} else {
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gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2);
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}
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} else if (op == 13) {
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} else {
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if (size == 1) {
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gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2);
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} else {
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gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2);
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}
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} else {
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TCGv_ptr fpstatus = get_fpstatus_ptr(1);
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gen_helper_vfp_muls(tmp, tmp, tmp2, fpstatus);
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tcg_temp_free_ptr(fpstatus);
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}
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tcg_temp_free_i32(tmp2);
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if (op < 8) {
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/* Accumulate. */
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tmp2 = neon_load_reg(rd, pass);
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switch (op) {
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case 1:
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{
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TCGv_ptr fpstatus = get_fpstatus_ptr(1);
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gen_helper_vfp_adds(tmp, tmp, tmp2, fpstatus);
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tcg_temp_free_ptr(fpstatus);
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break;
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}
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case 5:
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{
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TCGv_ptr fpstatus = get_fpstatus_ptr(1);
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gen_helper_vfp_subs(tmp, tmp2, tmp, fpstatus);
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tcg_temp_free_ptr(fpstatus);
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break;
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}
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default:
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abort();
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}
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tcg_temp_free_i32(tmp2);
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}
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neon_store_reg(rd, pass, tmp);
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}
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break;
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