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Hexagon (target/hexagon) compile all debug code 

Change #if HEX_DEBUG to if (HEX_DEBUG) so the debug code doesn't bit rot

Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-17-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Taylor Simpson 2021-04-08 20:07:44 -05:00 committed by Richard Henderson
parent a33872eb53
commit 85580a6557
6 changed files with 81 additions and 94 deletions
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20
target/hexagon/genptr.c
View File

@ -42,7 +42,7 @@ static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot)
tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot); tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot);
tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], slot_mask, zero, tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], slot_mask, zero,
val, hex_new_value[rnum]); val, hex_new_value[rnum]);
#if HEX_DEBUG if (HEX_DEBUG) {
/* /*
* Do this so HELPER(debug_commit_end) will know * Do this so HELPER(debug_commit_end) will know
* *
@ -52,7 +52,7 @@ static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot)
*/ */
tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero); tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero);
tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask); tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask);
#endif }
tcg_temp_free(zero); tcg_temp_free(zero);
tcg_temp_free(slot_mask); tcg_temp_free(slot_mask);
@ -61,10 +61,10 @@ static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot)
static inline void gen_log_reg_write(int rnum, TCGv val) static inline void gen_log_reg_write(int rnum, TCGv val)
{ {
tcg_gen_mov_tl(hex_new_value[rnum], val); tcg_gen_mov_tl(hex_new_value[rnum], val);
#if HEX_DEBUG if (HEX_DEBUG) {
/* Do this so HELPER(debug_commit_end) will know */ /* Do this so HELPER(debug_commit_end) will know */
tcg_gen_movi_tl(hex_reg_written[rnum], 1); tcg_gen_movi_tl(hex_reg_written[rnum], 1);
#endif }
} }
static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, int slot) static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, int slot)
@ -84,7 +84,7 @@ static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, int slot)
tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum + 1], tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum + 1],
slot_mask, zero, slot_mask, zero,
val32, hex_new_value[rnum + 1]); val32, hex_new_value[rnum + 1]);
#if HEX_DEBUG if (HEX_DEBUG) {
/* /*
* Do this so HELPER(debug_commit_end) will know * Do this so HELPER(debug_commit_end) will know
* *
@ -96,7 +96,7 @@ static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, int slot)
tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask); tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask);
tcg_gen_or_tl(hex_reg_written[rnum + 1], hex_reg_written[rnum + 1], tcg_gen_or_tl(hex_reg_written[rnum + 1], hex_reg_written[rnum + 1],
slot_mask); slot_mask);
#endif }
tcg_temp_free(val32); tcg_temp_free(val32);
tcg_temp_free(zero); tcg_temp_free(zero);
@ -107,17 +107,17 @@ static void gen_log_reg_write_pair(int rnum, TCGv_i64 val)
{ {
/* Low word */ /* Low word */
tcg_gen_extrl_i64_i32(hex_new_value[rnum], val); tcg_gen_extrl_i64_i32(hex_new_value[rnum], val);
#if HEX_DEBUG if (HEX_DEBUG) {
/* Do this so HELPER(debug_commit_end) will know */ /* Do this so HELPER(debug_commit_end) will know */
tcg_gen_movi_tl(hex_reg_written[rnum], 1); tcg_gen_movi_tl(hex_reg_written[rnum], 1);
#endif }
/* High word */ /* High word */
tcg_gen_extrh_i64_i32(hex_new_value[rnum + 1], val); tcg_gen_extrh_i64_i32(hex_new_value[rnum + 1], val);
#if HEX_DEBUG if (HEX_DEBUG) {
/* Do this so HELPER(debug_commit_end) will know */ /* Do this so HELPER(debug_commit_end) will know */
tcg_gen_movi_tl(hex_reg_written[rnum + 1], 1); tcg_gen_movi_tl(hex_reg_written[rnum + 1], 1);
#endif }
} }
static inline void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val) static inline void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val)

2
target/hexagon/helper.h
View File

@ -19,11 +19,9 @@
#include "helper_protos_generated.h.inc" #include "helper_protos_generated.h.inc"
DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_RETURN, noreturn, env, i32) DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_RETURN, noreturn, env, i32)
#if HEX_DEBUG
DEF_HELPER_1(debug_start_packet, void, env) DEF_HELPER_1(debug_start_packet, void, env)
DEF_HELPER_FLAGS_3(debug_check_store_width, TCG_CALL_NO_WG, void, env, int, int) DEF_HELPER_FLAGS_3(debug_check_store_width, TCG_CALL_NO_WG, void, env, int, int)
DEF_HELPER_FLAGS_3(debug_commit_end, TCG_CALL_NO_WG, void, env, int, int) DEF_HELPER_FLAGS_3(debug_commit_end, TCG_CALL_NO_WG, void, env, int, int)
#endif
DEF_HELPER_2(commit_store, void, env, int) DEF_HELPER_2(commit_store, void, env, int)
DEF_HELPER_FLAGS_4(fcircadd, TCG_CALL_NO_RWG_SE, s32, s32, s32, s32, s32) DEF_HELPER_FLAGS_4(fcircadd, TCG_CALL_NO_RWG_SE, s32, s32, s32, s32, s32)

11
target/hexagon/internal.h
View File

@ -22,11 +22,12 @@
* Change HEX_DEBUG to 1 to turn on debugging output * Change HEX_DEBUG to 1 to turn on debugging output
*/ */
#define HEX_DEBUG 0 #define HEX_DEBUG 0
#if HEX_DEBUG #define HEX_DEBUG_LOG(...) \
#define HEX_DEBUG_LOG(...) qemu_log(__VA_ARGS__) do { \
#else if (HEX_DEBUG) { \
#define HEX_DEBUG_LOG(...) do { } while (0) qemu_log(__VA_ARGS__); \
#endif } \
} while (0)
int hexagon_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int hexagon_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int hexagon_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); int hexagon_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);

10
target/hexagon/op_helper.c
View File

@ -56,10 +56,10 @@ static void log_reg_write(CPUHexagonState *env, int rnum,
HEX_DEBUG_LOG("\n"); HEX_DEBUG_LOG("\n");
env->new_value[rnum] = val; env->new_value[rnum] = val;
#if HEX_DEBUG if (HEX_DEBUG) {
/* Do this so HELPER(debug_commit_end) will know */ /* Do this so HELPER(debug_commit_end) will know */
env->reg_written[rnum] = 1; env->reg_written[rnum] = 1;
#endif }
} }
static void log_pred_write(CPUHexagonState *env, int pnum, target_ulong val) static void log_pred_write(CPUHexagonState *env, int pnum, target_ulong val)
@ -117,7 +117,6 @@ static void write_new_pc(CPUHexagonState *env, target_ulong addr)
} }
} }
#if HEX_DEBUG
/* Handy place to set a breakpoint */ /* Handy place to set a breakpoint */
void HELPER(debug_start_packet)(CPUHexagonState *env) void HELPER(debug_start_packet)(CPUHexagonState *env)
{ {
@ -128,14 +127,12 @@ void HELPER(debug_start_packet)(CPUHexagonState *env)
env->reg_written[i] = 0; env->reg_written[i] = 0;
} }
} }
#endif
static int32_t new_pred_value(CPUHexagonState *env, int pnum) static int32_t new_pred_value(CPUHexagonState *env, int pnum)
{ {
return env->new_pred_value[pnum]; return env->new_pred_value[pnum];
} }
#if HEX_DEBUG
/* Checks for bookkeeping errors between disassembly context and runtime */ /* Checks for bookkeeping errors between disassembly context and runtime */
void HELPER(debug_check_store_width)(CPUHexagonState *env, int slot, int check) void HELPER(debug_check_store_width)(CPUHexagonState *env, int slot, int check)
{ {
@ -145,7 +142,6 @@ void HELPER(debug_check_store_width)(CPUHexagonState *env, int slot, int check)
g_assert_not_reached(); g_assert_not_reached();
} }
} }
#endif
void HELPER(commit_store)(CPUHexagonState *env, int slot_num) void HELPER(commit_store)(CPUHexagonState *env, int slot_num)
{ {
@ -171,7 +167,6 @@ void HELPER(commit_store)(CPUHexagonState *env, int slot_num)
} }
} }
#if HEX_DEBUG
static void print_store(CPUHexagonState *env, int slot) static void print_store(CPUHexagonState *env, int slot)
{ {
if (!(env->slot_cancelled & (1 << slot))) { if (!(env->slot_cancelled & (1 << slot))) {
@ -255,7 +250,6 @@ void HELPER(debug_commit_end)(CPUHexagonState *env, int has_st0, int has_st1)
env->gpr[HEX_REG_QEMU_INSN_CNT]); env->gpr[HEX_REG_QEMU_INSN_CNT]);
} }
#endif
static int32_t fcircadd_v4(int32_t RxV, int32_t offset, int32_t M, int32_t CS) static int32_t fcircadd_v4(int32_t RxV, int32_t offset, int32_t M, int32_t CS)
{ {

42
target/hexagon/translate.c
View File

@ -35,9 +35,7 @@ TCGv hex_this_PC;
TCGv hex_slot_cancelled; TCGv hex_slot_cancelled;
TCGv hex_branch_taken; TCGv hex_branch_taken;
TCGv hex_new_value[TOTAL_PER_THREAD_REGS]; TCGv hex_new_value[TOTAL_PER_THREAD_REGS];
#if HEX_DEBUG
TCGv hex_reg_written[TOTAL_PER_THREAD_REGS]; TCGv hex_reg_written[TOTAL_PER_THREAD_REGS];
#endif
TCGv hex_new_pred_value[NUM_PREGS]; TCGv hex_new_pred_value[NUM_PREGS];
TCGv hex_pred_written; TCGv hex_pred_written;
TCGv hex_store_addr[STORES_MAX]; TCGv hex_store_addr[STORES_MAX];
@ -90,7 +88,6 @@ static void gen_exception_end_tb(DisasContext *ctx, int excp)
} }
#if HEX_DEBUG
#define PACKET_BUFFER_LEN 1028 #define PACKET_BUFFER_LEN 1028
static void print_pkt(Packet *pkt) static void print_pkt(Packet *pkt)
{ {
@ -99,10 +96,12 @@ static void print_pkt(Packet *pkt)
HEX_DEBUG_LOG("%s", buf->str); HEX_DEBUG_LOG("%s", buf->str);
g_string_free(buf, true); g_string_free(buf, true);
} }
#define HEX_DEBUG_PRINT_PKT(pkt) print_pkt(pkt) #define HEX_DEBUG_PRINT_PKT(pkt) \
#else do { \
#define HEX_DEBUG_PRINT_PKT(pkt) /* nothing */ if (HEX_DEBUG) { \
#endif print_pkt(pkt); \
} \
} while (0)
static int read_packet_words(CPUHexagonState *env, DisasContext *ctx, static int read_packet_words(CPUHexagonState *env, DisasContext *ctx,
uint32_t words[]) uint32_t words[])
@ -179,11 +178,11 @@ static void gen_start_packet(DisasContext *ctx, Packet *pkt)
tcg_gen_movi_tl(hex_pkt_has_store_s1, pkt->pkt_has_store_s1); tcg_gen_movi_tl(hex_pkt_has_store_s1, pkt->pkt_has_store_s1);
ctx->s1_store_processed = false; ctx->s1_store_processed = false;
#if HEX_DEBUG if (HEX_DEBUG) {
/* Handy place to set a breakpoint before the packet executes */ /* Handy place to set a breakpoint before the packet executes */
gen_helper_debug_start_packet(cpu_env); gen_helper_debug_start_packet(cpu_env);
tcg_gen_movi_tl(hex_this_PC, ctx->base.pc_next); tcg_gen_movi_tl(hex_this_PC, ctx->base.pc_next);
#endif }
/* Initialize the runtime state for packet semantics */ /* Initialize the runtime state for packet semantics */
if (need_pc(pkt)) { if (need_pc(pkt)) {
@ -308,10 +307,11 @@ static void gen_pred_writes(DisasContext *ctx, Packet *pkt)
for (i = 0; i < ctx->preg_log_idx; i++) { for (i = 0; i < ctx->preg_log_idx; i++) {
int pred_num = ctx->preg_log[i]; int pred_num = ctx->preg_log[i];
tcg_gen_mov_tl(hex_pred[pred_num], hex_new_pred_value[pred_num]); tcg_gen_mov_tl(hex_pred[pred_num], hex_new_pred_value[pred_num]);
#if HEX_DEBUG if (HEX_DEBUG) {
/* Do this so HELPER(debug_commit_end) will know */ /* Do this so HELPER(debug_commit_end) will know */
tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << pred_num); tcg_gen_ori_tl(hex_pred_written, hex_pred_written,
#endif 1 << pred_num);
}
} }
} }
@ -322,13 +322,13 @@ static void gen_pred_writes(DisasContext *ctx, Packet *pkt)
static void gen_check_store_width(DisasContext *ctx, int slot_num) static void gen_check_store_width(DisasContext *ctx, int slot_num)
{ {
#if HEX_DEBUG if (HEX_DEBUG) {
TCGv slot = tcg_const_tl(slot_num); TCGv slot = tcg_const_tl(slot_num);
TCGv check = tcg_const_tl(ctx->store_width[slot_num]); TCGv check = tcg_const_tl(ctx->store_width[slot_num]);
gen_helper_debug_check_store_width(cpu_env, slot, check); gen_helper_debug_check_store_width(cpu_env, slot, check);
tcg_temp_free(slot); tcg_temp_free(slot);
tcg_temp_free(check); tcg_temp_free(check);
#endif }
} }
static bool slot_is_predicated(Packet *pkt, int slot_num) static bool slot_is_predicated(Packet *pkt, int slot_num)
@ -482,8 +482,7 @@ static void gen_commit_packet(DisasContext *ctx, Packet *pkt)
process_store_log(ctx, pkt); process_store_log(ctx, pkt);
process_dczeroa(ctx, pkt); process_dczeroa(ctx, pkt);
update_exec_counters(ctx, pkt); update_exec_counters(ctx, pkt);
#if HEX_DEBUG if (HEX_DEBUG) {
{
TCGv has_st0 = TCGv has_st0 =
tcg_const_tl(pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa); tcg_const_tl(pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa);
TCGv has_st1 = TCGv has_st1 =
@ -495,7 +494,6 @@ static void gen_commit_packet(DisasContext *ctx, Packet *pkt)
tcg_temp_free(has_st0); tcg_temp_free(has_st0);
tcg_temp_free(has_st1); tcg_temp_free(has_st1);
} }
#endif
if (pkt->pkt_has_cof) { if (pkt->pkt_has_cof) {
gen_end_tb(ctx); gen_end_tb(ctx);
@ -655,9 +653,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
#define NAME_LEN 64 #define NAME_LEN 64
static char new_value_names[TOTAL_PER_THREAD_REGS][NAME_LEN]; static char new_value_names[TOTAL_PER_THREAD_REGS][NAME_LEN];
#if HEX_DEBUG
static char reg_written_names[TOTAL_PER_THREAD_REGS][NAME_LEN]; static char reg_written_names[TOTAL_PER_THREAD_REGS][NAME_LEN];
#endif
static char new_pred_value_names[NUM_PREGS][NAME_LEN]; static char new_pred_value_names[NUM_PREGS][NAME_LEN];
static char store_addr_names[STORES_MAX][NAME_LEN]; static char store_addr_names[STORES_MAX][NAME_LEN];
static char store_width_names[STORES_MAX][NAME_LEN]; static char store_width_names[STORES_MAX][NAME_LEN];
@ -670,11 +666,11 @@ void hexagon_translate_init(void)
opcode_init(); opcode_init();
#if HEX_DEBUG if (HEX_DEBUG) {
if (!qemu_logfile) { if (!qemu_logfile) {
qemu_set_log(qemu_loglevel); qemu_set_log(qemu_loglevel);
} }
#endif }
for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) { for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) {
hex_gpr[i] = tcg_global_mem_new(cpu_env, hex_gpr[i] = tcg_global_mem_new(cpu_env,
@ -686,13 +682,13 @@ void hexagon_translate_init(void)
offsetof(CPUHexagonState, new_value[i]), offsetof(CPUHexagonState, new_value[i]),
new_value_names[i]); new_value_names[i]);
#if HEX_DEBUG if (HEX_DEBUG) {
snprintf(reg_written_names[i], NAME_LEN, "reg_written_%s", snprintf(reg_written_names[i], NAME_LEN, "reg_written_%s",
hexagon_regnames[i]); hexagon_regnames[i]);
hex_reg_written[i] = tcg_global_mem_new(cpu_env, hex_reg_written[i] = tcg_global_mem_new(cpu_env,
offsetof(CPUHexagonState, reg_written[i]), offsetof(CPUHexagonState, reg_written[i]),
reg_written_names[i]); reg_written_names[i]);
#endif }
} }
for (i = 0; i < NUM_PREGS; i++) { for (i = 0; i < NUM_PREGS; i++) {
hex_pred[i] = tcg_global_mem_new(cpu_env, hex_pred[i] = tcg_global_mem_new(cpu_env,

2
target/hexagon/translate.h
View File

@ -41,11 +41,9 @@ typedef struct DisasContext {
static inline void ctx_log_reg_write(DisasContext *ctx, int rnum) static inline void ctx_log_reg_write(DisasContext *ctx, int rnum)
{ {
#if HEX_DEBUG
if (test_bit(rnum, ctx->regs_written)) { if (test_bit(rnum, ctx->regs_written)) {
HEX_DEBUG_LOG("WARNING: Multiple writes to r%d\n", rnum); HEX_DEBUG_LOG("WARNING: Multiple writes to r%d\n", rnum);
} }
#endif
ctx->reg_log[ctx->reg_log_idx] = rnum; ctx->reg_log[ctx->reg_log_idx] = rnum;
ctx->reg_log_idx++; ctx->reg_log_idx++;
set_bit(rnum, ctx->regs_written); set_bit(rnum, ctx->regs_written);