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target/hppa patches 

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Merge tag 'hppa-fixes-pull-request' of https://github.com/hdeller/qemu-hppa into staging

target/hppa patches

# gpg: Signature made Mon 19 Dec 2022 22:27:31 GMT
# gpg:                using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F
# gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown]
# gpg:                 aka "Helge Deller <deller@kernel.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 4544 8228 2CD9 10DB EF3D  25F8 3E5F 3D04 A7A2 4603
#      Subkey fingerprint: BCE9 123E 1AD2 9F07 C049  BBDE F712 B510 A23A 0F5F

* tag 'hppa-fixes-pull-request' of https://github.com/hdeller/qemu-hppa:
  target/hppa: Fix fid instruction emulation
  target/hppa: Generate illegal instruction exception for 64-bit instructions

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2022-12-20 15:32:27 +00:00
parent 33698d3abf 59f8c04b22
commit 8540a1f695
2 changed files with 22 additions and 6 deletions
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5
target/hppa/insns.decode
View File

@ -388,10 +388,7 @@ fmpyfadd_d 101110 rm1:5 rm2:5 ... 0 1 ..0 0 0 neg:1 t:5 ra3=%rc32
# Floating point class 0
# FID. With r = t = 0, which via fcpy puts 0 into fr0.
# This is machine/revision = 0, which is reserved for simulator.
fcpy_f 001100 00000 00000 00000 000000 00000 \
&fclass01 r=0 t=0
fid_f 001100 00000 00000 000 00 000000 00000
fcpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_0
fabs_f 001100 ..... ..... 011 00 ...... ..... @f0c_0

23
target/hppa/translate.c
View File

@ -2899,14 +2899,22 @@ static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf *a)
static bool trans_ld(DisasContext *ctx, arg_ldst *a)
{
return do_load(ctx, a->t, a->b, a->x, a->scale ? a->size : 0,
if (unlikely(TARGET_REGISTER_BITS == 32 && a->size > MO_32)) {
return gen_illegal(ctx);
} else {
return do_load(ctx, a->t, a->b, a->x, a->scale ? a->size : 0,
a->disp, a->sp, a->m, a->size | MO_TE);
}
}
static bool trans_st(DisasContext *ctx, arg_ldst *a)
{
assert(a->x == 0 && a->scale == 0);
return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size | MO_TE);
if (unlikely(TARGET_REGISTER_BITS == 32 && a->size > MO_32)) {
return gen_illegal(ctx);
} else {
return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size | MO_TE);
}
}
static bool trans_ldc(DisasContext *ctx, arg_ldst *a)
@ -3614,6 +3622,17 @@ static void gen_fcpy_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src)
tcg_gen_mov_i32(dst, src);
}
static bool trans_fid_f(DisasContext *ctx, arg_fid_f *a)
{
nullify_over(ctx);
#if TARGET_REGISTER_BITS == 64
save_frd(0, tcg_const_i64(0x13080000000000ULL)); /* PA8700 (PCX-W2) */
#else
save_frd(0, tcg_const_i64(0x0f080000000000ULL)); /* PA7300LC (PCX-L2) */
#endif
return nullify_end(ctx);
}
static bool trans_fcpy_f(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_wew(ctx, a->t, a->r, gen_fcpy_f);