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target/arm: Convert Cryptographic AES to decodetree 

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240524232121.284515-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-05-24 16:20:23 -07:00 committed by Peter Maydell
parent a11efe30b9
commit 8424801eb5
2 changed files with 54 additions and 53 deletions
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21
target/arm/tcg/a64.decode
View File

@ -19,11 +19,17 @@
# This file is processed by scripts/decodetree.py
#
&r rn
&ri rd imm
&rri_sf rd rn imm sf
&i imm
%rd 0:5
&r rn
&ri rd imm
&rri_sf rd rn imm sf
&i imm
&qrr_e q rd rn esz
&qrrr_e q rd rn rm esz
@rr_q1e0 ........ ........ ...... rn:5 rd:5 &qrr_e q=1 esz=0
@r2r_q1e0 ........ ........ ...... rm:5 rd:5 &qrrr_e rn=%rd q=1 esz=0
### Data Processing - Immediate
@ -590,3 +596,10 @@ CPYFE 00 011 0 01100 ..... .... 01 ..... ..... @cpy
CPYP 00 011 1 01000 ..... .... 01 ..... ..... @cpy
CPYM 00 011 1 01010 ..... .... 01 ..... ..... @cpy
CPYE 00 011 1 01100 ..... .... 01 ..... ..... @cpy
### Cryptographic AES
AESE 01001110 00 10100 00100 10 ..... ..... @r2r_q1e0
AESD 01001110 00 10100 00101 10 ..... ..... @r2r_q1e0
AESMC 01001110 00 10100 00110 10 ..... ..... @rr_q1e0
AESIMC 01001110 00 10100 00111 10 ..... ..... @rr_q1e0

86
target/arm/tcg/translate-a64.c
View File

@ -1313,6 +1313,34 @@ bool sme_enabled_check_with_svcr(DisasContext *s, unsigned req)
return true;
}
/*
* Expanders for AdvSIMD translation functions.
*/
static bool do_gvec_op2_ool(DisasContext *s, arg_qrr_e *a, int data,
gen_helper_gvec_2 *fn)
{
if (!a->q && a->esz == MO_64) {
return false;
}
if (fp_access_check(s)) {
gen_gvec_op2_ool(s, a->q, a->rd, a->rn, data, fn);
}
return true;
}
static bool do_gvec_op3_ool(DisasContext *s, arg_qrrr_e *a, int data,
gen_helper_gvec_3 *fn)
{
if (!a->q && a->esz == MO_64) {
return false;
}
if (fp_access_check(s)) {
gen_gvec_op3_ool(s, a->q, a->rd, a->rn, a->rm, data, fn);
}
return true;
}
/*
* This utility function is for doing register extension with an
* optional shift. You will likely want to pass a temporary for the
@ -4560,6 +4588,15 @@ static bool trans_EXTR(DisasContext *s, arg_extract *a)
return true;
}
/*
* Cryptographic AES
*/
TRANS_FEAT(AESE, aa64_aes, do_gvec_op3_ool, a, 0, gen_helper_crypto_aese)
TRANS_FEAT(AESD, aa64_aes, do_gvec_op3_ool, a, 0, gen_helper_crypto_aesd)
TRANS_FEAT(AESMC, aa64_aes, do_gvec_op2_ool, a, 0, gen_helper_crypto_aesmc)
TRANS_FEAT(AESIMC, aa64_aes, do_gvec_op2_ool, a, 0, gen_helper_crypto_aesimc)
/* Shift a TCGv src by TCGv shift_amount, put result in dst.
* Note that it is the caller's responsibility to ensure that the
* shift amount is in range (ie 0..31 or 0..63) and provide the ARM
@ -13460,54 +13497,6 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
}
}
/* Crypto AES
* 31 24 23 22 21 17 16 12 11 10 9 5 4 0
* +-----------------+------+-----------+--------+-----+------+------+
* | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
* +-----------------+------+-----------+--------+-----+------+------+
*/
static void disas_crypto_aes(DisasContext *s, uint32_t insn)
{
int size = extract32(insn, 22, 2);
int opcode = extract32(insn, 12, 5);
int rn = extract32(insn, 5, 5);
int rd = extract32(insn, 0, 5);
gen_helper_gvec_2 *genfn2 = NULL;
gen_helper_gvec_3 *genfn3 = NULL;
if (!dc_isar_feature(aa64_aes, s) || size != 0) {
unallocated_encoding(s);
return;
}
switch (opcode) {
case 0x4: /* AESE */
genfn3 = gen_helper_crypto_aese;
break;
case 0x6: /* AESMC */
genfn2 = gen_helper_crypto_aesmc;
break;
case 0x5: /* AESD */
genfn3 = gen_helper_crypto_aesd;
break;
case 0x7: /* AESIMC */
genfn2 = gen_helper_crypto_aesimc;
break;
default:
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
if (genfn2) {
gen_gvec_op2_ool(s, true, rd, rn, 0, genfn2);
} else {
gen_gvec_op3_ool(s, true, rd, rd, rn, 0, genfn3);
}
}
/* Crypto three-reg SHA
* 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
* +-----------------+------+---+------+---+--------+-----+------+------+
@ -13917,7 +13906,6 @@ static const AArch64DecodeTable data_proc_simd[] = {
{ 0x5e000400, 0xdfe08400, disas_simd_scalar_copy },
{ 0x5f000000, 0xdf000400, disas_simd_indexed }, /* scalar indexed */
{ 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm },
{ 0x4e280800, 0xff3e0c00, disas_crypto_aes },
{ 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha },
{ 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha },
{ 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512 },