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Compile isa_mmio only once 

Push TARGET_WORDS_BIGENDIAN dependency to board level.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl 2010-03-21 19:47:09 +00:00
parent 7161e5710b
commit 84108e128e
14 changed files with 96 additions and 36 deletions
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1
Makefile.objs
View File

@ -131,6 +131,7 @@ hw-obj-y += loader.o
hw-obj-y += virtio.o virtio-console.o
hw-obj-y += fw_cfg.o
hw-obj-y += watchdog.o
hw-obj-$(CONFIG_ISA_MMIO) += isa_mmio.o
hw-obj-$(CONFIG_ECC) += ecc.o
hw-obj-$(CONFIG_NAND) += nand.o

1
Makefile.target
View File

@ -168,7 +168,6 @@ obj-y += qemu-timer.o
obj-y += virtio-blk.o virtio-balloon.o virtio-net.o virtio-pci.o virtio-serial-bus.o
obj-y += rwhandler.o
obj-$(CONFIG_KVM) += kvm.o kvm-all.o
obj-$(CONFIG_ISA_MMIO) += isa_mmio.o
LIBS+=-lz
sound-obj-y =

6
hw/gt64xxx.c
View File

@ -297,7 +297,11 @@ static void gt64120_pci_mapping(GT64120State *s)
s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
isa_mem_base = s->PCI0IO_start;
isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length);
#ifdef TARGET_WORDS_BIGENDIAN
isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length, 1);
#else
isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length, 0);
#endif
}
}

2
hw/isa.h
View File

@ -32,7 +32,7 @@ ISADevice *isa_create_simple(const char *name);
extern target_phys_addr_t isa_mem_base;
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be);
/* dma.c */
int DMA_get_channel_mode (int nchan);

85
hw/isa_mmio.c
View File

@ -31,21 +31,29 @@ static void isa_mmio_writeb (void *opaque, target_phys_addr_t addr,
cpu_outb(addr & IOPORTS_MASK, val);
}
static void isa_mmio_writew (void *opaque, target_phys_addr_t addr,
uint32_t val)
static void isa_mmio_writew_be(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap16(val);
#endif
cpu_outw(addr & IOPORTS_MASK, val);
}
static void isa_mmio_writel (void *opaque, target_phys_addr_t addr,
uint32_t val)
static void isa_mmio_writew_le(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
cpu_outw(addr & IOPORTS_MASK, val);
}
static void isa_mmio_writel_be(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap32(val);
#endif
cpu_outl(addr & IOPORTS_MASK, val);
}
static void isa_mmio_writel_le(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
cpu_outl(addr & IOPORTS_MASK, val);
}
@ -57,47 +65,78 @@ static uint32_t isa_mmio_readb (void *opaque, target_phys_addr_t addr)
return val;
}
static uint32_t isa_mmio_readw (void *opaque, target_phys_addr_t addr)
static uint32_t isa_mmio_readw_be(void *opaque, target_phys_addr_t addr)
{
uint32_t val;
val = cpu_inw(addr & IOPORTS_MASK);
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap16(val);
#endif
return val;
}
static uint32_t isa_mmio_readl (void *opaque, target_phys_addr_t addr)
static uint32_t isa_mmio_readw_le(void *opaque, target_phys_addr_t addr)
{
uint32_t val;
val = cpu_inw(addr & IOPORTS_MASK);
return val;
}
static uint32_t isa_mmio_readl_be(void *opaque, target_phys_addr_t addr)
{
uint32_t val;
val = cpu_inl(addr & IOPORTS_MASK);
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap32(val);
#endif
return val;
}
static CPUWriteMemoryFunc * const isa_mmio_write[] = {
static uint32_t isa_mmio_readl_le(void *opaque, target_phys_addr_t addr)
{
uint32_t val;
val = cpu_inl(addr & IOPORTS_MASK);
return val;
}
static CPUWriteMemoryFunc * const isa_mmio_write_be[] = {
&isa_mmio_writeb,
&isa_mmio_writew,
&isa_mmio_writel,
&isa_mmio_writew_be,
&isa_mmio_writel_be,
};
static CPUReadMemoryFunc * const isa_mmio_read[] = {
static CPUReadMemoryFunc * const isa_mmio_read_be[] = {
&isa_mmio_readb,
&isa_mmio_readw,
&isa_mmio_readl,
&isa_mmio_readw_be,
&isa_mmio_readl_be,
};
static CPUWriteMemoryFunc * const isa_mmio_write_le[] = {
&isa_mmio_writeb,
&isa_mmio_writew_le,
&isa_mmio_writel_le,
};
static CPUReadMemoryFunc * const isa_mmio_read_le[] = {
&isa_mmio_readb,
&isa_mmio_readw_le,
&isa_mmio_readl_le,
};
static int isa_mmio_iomemtype = 0;
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size)
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be)
{
if (!isa_mmio_iomemtype) {
isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read,
isa_mmio_write, NULL);
if (be) {
isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read_be,
isa_mmio_write_be,
NULL);
} else {
isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read_le,
isa_mmio_write_le,
NULL);
}
}
cpu_register_physical_memory(base, size, isa_mmio_iomemtype);
}

7
hw/mips_jazz.c
View File

@ -192,7 +192,12 @@ void mips_jazz_init (ram_addr_t ram_size,
pcspk_init(pit);
/* ISA IO space at 0x90000000 */
isa_mmio_init(0x90000000, 0x01000000);
#ifdef TARGET_WORDS_BIGENDIAN
isa_mmio_init(0x90000000, 0x01000000, 1);
#else
isa_mmio_init(0x90000000, 0x01000000, 0);
#endif
isa_mem_base = 0x11000000;
/* Video card */

6
hw/mips_mipssim.c
View File

@ -182,7 +182,11 @@ mips_mipssim_init (ram_addr_t ram_size,
cpu_mips_clock_init(env);
/* Register 64 KB of ISA IO space at 0x1fd00000. */
isa_mmio_init(0x1fd00000, 0x00010000);
#ifdef TARGET_WORDS_BIGENDIAN
isa_mmio_init(0x1fd00000, 0x00010000, 1);
#else
isa_mmio_init(0x1fd00000, 0x00010000, 0);
#endif
/* A single 16450 sits at offset 0x3f8. It is attached to
MIPS CPU INT2, which is interrupt 4. */

6
hw/mips_r4k.c
View File

@ -261,7 +261,11 @@ void mips_r4k_init (ram_addr_t ram_size,
rtc_state = rtc_init(2000);
/* Register 64 KB of ISA IO space at 0x14000000 */
isa_mmio_init(0x14000000, 0x00010000);
#ifdef TARGET_WORDS_BIGENDIAN
isa_mmio_init(0x14000000, 0x00010000, 1);
#else
isa_mmio_init(0x14000000, 0x00010000, 0);
#endif
isa_mem_base = 0x10000000;
pit = pit_init(0x40, i8259[0]);

2
hw/ppc440.c
View File

@ -85,7 +85,7 @@ CPUState *ppc440ep_init(ram_addr_t *ram_size, PCIBus **pcip,
if (!*pcip)
printf("couldn't create PCI controller!\n");
isa_mmio_init(PPC440EP_PCI_IO, PPC440EP_PCI_IOLEN);
isa_mmio_init(PPC440EP_PCI_IO, PPC440EP_PCI_IOLEN, 1);
if (serial_hds[0] != NULL) {
serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,

2
hw/ppc_newworld.c
View File

@ -291,7 +291,7 @@ static void ppc_core99_init (ram_addr_t ram_size,
isa_mem_base = 0x80000000;
/* Register 8 MB of ISA IO space */
isa_mmio_init(0xf2000000, 0x00800000);
isa_mmio_init(0xf2000000, 0x00800000, 1);
/* UniN init */
unin_memory = cpu_register_io_memory(unin_read, unin_write, NULL);

2
hw/ppc_oldworld.c
View File

@ -304,7 +304,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size,
isa_mem_base = 0x80000000;
/* Register 2 MB of ISA IO space */
isa_mmio_init(0xfe000000, 0x00200000);
isa_mmio_init(0xfe000000, 0x00200000, 1);
/* XXX: we register only 1 output pin for heathrow PIC */
heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));

2
hw/ppce500_mpc8544ds.c
View File

@ -218,7 +218,7 @@ static void mpc8544ds_init(ram_addr_t ram_size,
if (!pci_bus)
printf("couldn't create PCI controller!\n");
isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN);
isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN, 1);
if (pci_bus) {
/* Register network interfaces. */

4
hw/sun4u.c
View File

@ -520,10 +520,10 @@ static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
region_num, addr);
switch (region_num) {
case 0:
isa_mmio_init(addr, 0x1000000);
isa_mmio_init(addr, 0x1000000, 1);
break;
case 1:
isa_mmio_init(addr, 0x800000);
isa_mmio_init(addr, 0x800000, 1);
break;
}
}

6
hw/versatile_pci.c
View File

@ -108,7 +108,11 @@ static void pci_vpb_map(SysBusDevice *dev, target_phys_addr_t base)
if (s->realview) {
/* IO memory area. */
isa_mmio_init(base + 0x03000000, 0x00100000);
#ifdef TARGET_WORDS_BIGENDIAN
isa_mmio_init(base + 0x03000000, 0x00100000, 1);
#else
isa_mmio_init(base + 0x03000000, 0x00100000, 0);
#endif
}
}