mirror of https://github.com/xemu-project/xemu.git
hw/intc/arm_gicv3: Add external IRQ lines for NMI
Augment the GICv3's QOM device interface by adding one new set of sysbus IRQ line, to signal NMI to each CPU. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-11-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -299,6 +299,12 @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
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for (i = 0; i < s->num_cpu; i++) {
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sysbus_init_irq(sbd, &s->cpu[i].parent_vfiq);
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}
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for (i = 0; i < s->num_cpu; i++) {
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sysbus_init_irq(sbd, &s->cpu[i].parent_nmi);
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}
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for (i = 0; i < s->num_cpu; i++) {
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sysbus_init_irq(sbd, &s->cpu[i].parent_vnmi);
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}
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memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s,
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"gicv3_dist", 0x10000);
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@ -71,6 +71,8 @@ struct GICState {
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qemu_irq parent_fiq[GIC_NCPU];
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qemu_irq parent_virq[GIC_NCPU];
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qemu_irq parent_vfiq[GIC_NCPU];
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qemu_irq parent_nmi[GIC_NCPU];
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qemu_irq parent_vnmi[GIC_NCPU];
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qemu_irq maintenance_irq[GIC_NCPU];
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/* GICD_CTLR; for a GIC with the security extensions the NS banked version
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@ -155,6 +155,8 @@ struct GICv3CPUState {
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qemu_irq parent_fiq;
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qemu_irq parent_virq;
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qemu_irq parent_vfiq;
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qemu_irq parent_nmi;
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qemu_irq parent_vnmi;
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/* Redistributor */
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uint32_t level; /* Current IRQ level */
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