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hw/arm/mps3r: Add remaining devices
Add the remaining devices (or unimplemented-device stubs) for this board: SPI controllers, SCC, FPGAIO, I2S, RTC, the QSPI write-config block, and ethernet. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240206132931.38376-13-peter.maydell@linaro.org
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@ -40,7 +40,12 @@
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#include "hw/char/cmsdk-apb-uart.h"
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#include "hw/i2c/arm_sbcon_i2c.h"
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#include "hw/intc/arm_gicv3.h"
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#include "hw/misc/mps2-scc.h"
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#include "hw/misc/mps2-fpgaio.h"
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#include "hw/misc/unimp.h"
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#include "hw/net/lan9118.h"
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#include "hw/rtc/pl031.h"
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#include "hw/ssi/pl022.h"
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#include "hw/timer/cmsdk-apb-dualtimer.h"
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#include "hw/watchdog/cmsdk-apb-watchdog.h"
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@ -105,6 +110,11 @@ struct MPS3RMachineState {
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CMSDKAPBWatchdog watchdog;
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CMSDKAPBDualTimer dualtimer;
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ArmSbconI2CState i2c[5];
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PL022State spi[3];
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MPS2SCC scc;
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MPS2FPGAIO fpgaio;
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UnimplementedDeviceState i2s_audio;
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PL031State rtc;
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Clock *clk;
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};
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@ -178,6 +188,16 @@ static const RAMInfo an536_raminfo[] = {
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}
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};
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static const int an536_oscclk[] = {
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24000000, /* 24MHz reference for RTC and timers */
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50000000, /* 50MHz ACLK */
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50000000, /* 50MHz MCLK */
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50000000, /* 50MHz GPUCLK */
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24576000, /* 24.576MHz AUDCLK */
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23750000, /* 23.75MHz HDLCDCLK */
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100000000, /* 100MHz DDR4_REF_CLK */
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};
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static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
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const RAMInfo *raminfo)
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{
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@ -337,6 +357,7 @@ static void mps3r_common_init(MachineState *machine)
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MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
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MemoryRegion *sysmem = get_system_memory();
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DeviceState *gicdev;
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QList *oscclk;
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mms->clk = clock_new(OBJECT(machine), "CLK");
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clock_set_hz(mms->clk, CLK_FRQ);
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@ -480,6 +501,59 @@ static void mps3r_common_init(MachineState *machine)
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}
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}
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for (int i = 0; i < ARRAY_SIZE(mms->spi); i++) {
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g_autofree char *s = g_strdup_printf("spi%d", i);
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hwaddr baseaddr = 0xe0104000 + i * 0x1000;
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object_initialize_child(OBJECT(mms), s, &mms->spi[i], TYPE_PL022);
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sysbus_realize(SYS_BUS_DEVICE(&mms->spi[i]), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(&mms->spi[i]), 0, baseaddr);
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sysbus_connect_irq(SYS_BUS_DEVICE(&mms->spi[i]), 0,
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qdev_get_gpio_in(gicdev, 22 + i));
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}
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object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC);
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qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg0", 0);
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qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg4", 0x2);
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qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-aid", 0x00200008);
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qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-id", 0x41055360);
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oscclk = qlist_new();
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for (int i = 0; i < ARRAY_SIZE(an536_oscclk); i++) {
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qlist_append_int(oscclk, an536_oscclk[i]);
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}
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qdev_prop_set_array(DEVICE(&mms->scc), "oscclk", oscclk);
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sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(&mms->scc), 0, 0xe0200000);
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create_unimplemented_device("i2s-audio", 0xe0201000, 0x1000);
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object_initialize_child(OBJECT(mms), "fpgaio", &mms->fpgaio,
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TYPE_MPS2_FPGAIO);
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qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", an536_oscclk[1]);
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qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "num-leds", 10);
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qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-switches", true);
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qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-dbgctrl", false);
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sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0xe0202000);
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create_unimplemented_device("clcd", 0xe0209000, 0x1000);
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object_initialize_child(OBJECT(mms), "rtc", &mms->rtc, TYPE_PL031);
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sysbus_realize(SYS_BUS_DEVICE(&mms->rtc), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(&mms->rtc), 0, 0xe020a000);
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sysbus_connect_irq(SYS_BUS_DEVICE(&mms->rtc), 0,
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qdev_get_gpio_in(gicdev, 4));
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/*
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* In hardware this is a LAN9220; the LAN9118 is software compatible
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* except that it doesn't support the checksum-offload feature.
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*/
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lan9118_init(0xe0300000,
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qdev_get_gpio_in(gicdev, 18));
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create_unimplemented_device("usb", 0xe0301000, 0x1000);
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create_unimplemented_device("qspi-write-config", 0xe0600000, 0x1000);
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mms->bootinfo.ram_size = machine->ram_size;
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mms->bootinfo.board_id = -1;
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mms->bootinfo.loader_start = mmc->loader_start;
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