hw/timer/aspeed: Fix coding style

Fix coding style issues from checkpatch.pl

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Jamin Lin 2024-10-29 17:17:23 +08:00 committed by Cédric Le Goater
parent fc2693cc35
commit 82a919f8f1
1 changed files with 8 additions and 5 deletions

View File

@ -276,7 +276,8 @@ static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg,
old_reload = t->reload; old_reload = t->reload;
t->reload = calculate_min_ticks(t, value); t->reload = calculate_min_ticks(t, value);
/* If the reload value was not previously set, or zero, and /*
* If the reload value was not previously set, or zero, and
* the current value is valid, try to start the timer if it is * the current value is valid, try to start the timer if it is
* enabled. * enabled.
*/ */
@ -312,7 +313,8 @@ static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg,
} }
} }
/* Control register operations are broken out into helpers that can be /*
* Control register operations are broken out into helpers that can be
* explicitly called on aspeed_timer_reset(), but also from * explicitly called on aspeed_timer_reset(), but also from
* aspeed_timer_ctrl_op(). * aspeed_timer_ctrl_op().
*/ */
@ -396,7 +398,8 @@ static void aspeed_timer_set_ctrl(AspeedTimerCtrlState *s, uint32_t reg)
AspeedTimer *t; AspeedTimer *t;
const uint8_t enable_mask = BIT(op_enable); const uint8_t enable_mask = BIT(op_enable);
/* Handle a dependency between the 'enable' and remaining three /*
* Handle a dependency between the 'enable' and remaining three
* configuration bits - i.e. if more than one bit in the control set has * configuration bits - i.e. if more than one bit in the control set has
* changed, including the 'enable' bit, then we want either disable the * changed, including the 'enable' bit, then we want either disable the
* timer and perform configuration, or perform configuration and then * timer and perform configuration, or perform configuration and then
@ -582,7 +585,6 @@ static void aspeed_2600_timer_write(AspeedTimerCtrlState *s, hwaddr offset,
case 0x3C: case 0x3C:
aspeed_timer_set_ctrl(s, s->ctrl & ~tv); aspeed_timer_set_ctrl(s, s->ctrl & ~tv);
break; break;
case 0x38: case 0x38:
default: default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
@ -623,7 +625,8 @@ static void aspeed_timer_reset(DeviceState *dev)
for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
AspeedTimer *t = &s->timers[i]; AspeedTimer *t = &s->timers[i];
/* Explicitly call helpers to avoid any conditional behaviour through /*
* Explicitly call helpers to avoid any conditional behaviour through
* aspeed_timer_set_ctrl(). * aspeed_timer_set_ctrl().
*/ */
aspeed_timer_ctrl_enable(t, false); aspeed_timer_ctrl_enable(t, false);