mirror of https://github.com/xemu-project/xemu.git
target-mips: refactor c{, abs}.cond.fmt insns
Move all knowledge about coprocessor-checking and register numbering into the gen_cmp* helper functions. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Nathan Froyd
Aurelien Jarno
parent
e459440a89
commit
8153667c71
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@ -676,39 +676,6 @@ static inline int get_fp_bit (int cc)
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return 23;
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}
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#define FOP_CONDS(type, fmt, bits) \
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static inline void gen_cmp ## type ## _ ## fmt(int n, TCGv_i##bits a, \
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TCGv_i##bits b, int cc) \
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{ \
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switch (n) { \
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case 0: gen_helper_2i(cmp ## type ## _ ## fmt ## _f, a, b, cc); break;\
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case 1: gen_helper_2i(cmp ## type ## _ ## fmt ## _un, a, b, cc); break;\
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case 2: gen_helper_2i(cmp ## type ## _ ## fmt ## _eq, a, b, cc); break;\
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case 3: gen_helper_2i(cmp ## type ## _ ## fmt ## _ueq, a, b, cc); break;\
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case 4: gen_helper_2i(cmp ## type ## _ ## fmt ## _olt, a, b, cc); break;\
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case 5: gen_helper_2i(cmp ## type ## _ ## fmt ## _ult, a, b, cc); break;\
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case 6: gen_helper_2i(cmp ## type ## _ ## fmt ## _ole, a, b, cc); break;\
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case 7: gen_helper_2i(cmp ## type ## _ ## fmt ## _ule, a, b, cc); break;\
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case 8: gen_helper_2i(cmp ## type ## _ ## fmt ## _sf, a, b, cc); break;\
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case 9: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngle, a, b, cc); break;\
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case 10: gen_helper_2i(cmp ## type ## _ ## fmt ## _seq, a, b, cc); break;\
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case 11: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngl, a, b, cc); break;\
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case 12: gen_helper_2i(cmp ## type ## _ ## fmt ## _lt, a, b, cc); break;\
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case 13: gen_helper_2i(cmp ## type ## _ ## fmt ## _nge, a, b, cc); break;\
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case 14: gen_helper_2i(cmp ## type ## _ ## fmt ## _le, a, b, cc); break;\
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case 15: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngt, a, b, cc); break;\
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default: abort(); \
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} \
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}
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FOP_CONDS(, d, 64)
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FOP_CONDS(abs, d, 64)
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FOP_CONDS(, s, 32)
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FOP_CONDS(abs, s, 32)
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FOP_CONDS(, ps, 64)
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FOP_CONDS(abs, ps, 64)
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#undef FOP_CONDS
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/* Tests */
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static inline void gen_save_pc(target_ulong pc)
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{
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@ -849,6 +816,69 @@ static inline void check_mips_64(DisasContext *ctx)
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generate_exception(ctx, EXCP_RI);
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}
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/* Define small wrappers for gen_load_fpr* so that we have a uniform
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calling interface for 32 and 64-bit FPRs. No sense in changing
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all callers for gen_load_fpr32 when we need the CTX parameter for
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this one use. */
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#define gen_ldcmp_fpr32(ctx, x, y) gen_load_fpr32(x, y)
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#define gen_ldcmp_fpr64(ctx, x, y) gen_load_fpr64(ctx, x, y)
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#define FOP_CONDS(type, abs, fmt, ifmt, bits) \
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static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \
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int ft, int fs, int cc) \
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{ \
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TCGv_i##bits fp0 = tcg_temp_new_i##bits (); \
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TCGv_i##bits fp1 = tcg_temp_new_i##bits (); \
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switch (ifmt) { \
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case FMT_PS: \
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check_cp1_64bitmode(ctx); \
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break; \
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case FMT_D: \
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if (abs) { \
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check_cop1x(ctx); \
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} \
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check_cp1_registers(ctx, fs | ft); \
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break; \
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case FMT_S: \
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if (abs) { \
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check_cop1x(ctx); \
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} \
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break; \
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} \
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gen_ldcmp_fpr##bits (ctx, fp0, fs); \
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gen_ldcmp_fpr##bits (ctx, fp1, ft); \
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switch (n) { \
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case 0: gen_helper_2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); break;\
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case 1: gen_helper_2i(cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc); break;\
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case 2: gen_helper_2i(cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc); break;\
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case 3: gen_helper_2i(cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc); break;\
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case 4: gen_helper_2i(cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc); break;\
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case 5: gen_helper_2i(cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc); break;\
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case 6: gen_helper_2i(cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc); break;\
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case 7: gen_helper_2i(cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc); break;\
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case 8: gen_helper_2i(cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc); break;\
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case 9: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc); break;\
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case 10: gen_helper_2i(cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc); break;\
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case 11: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc); break;\
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case 12: gen_helper_2i(cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc); break;\
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case 13: gen_helper_2i(cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc); break;\
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case 14: gen_helper_2i(cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc); break;\
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case 15: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc); break;\
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default: abort(); \
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} \
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tcg_temp_free_i##bits (fp0); \
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tcg_temp_free_i##bits (fp1); \
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}
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FOP_CONDS(, 0, d, FMT_D, 64)
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FOP_CONDS(abs, 1, d, FMT_D, 64)
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FOP_CONDS(, 0, s, FMT_S, 32)
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FOP_CONDS(abs, 1, s, FMT_S, 32)
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FOP_CONDS(, 0, ps, FMT_PS, 64)
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FOP_CONDS(abs, 1, ps, FMT_PS, 64)
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#undef FOP_CONDS
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#undef gen_ldcmp_fpr32
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#undef gen_ldcmp_fpr64
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/* load/store instructions. */
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#define OP_LD(insn,fname) \
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static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
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@ -6480,22 +6510,12 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
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case OPC_CMP_NGE_S:
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case OPC_CMP_LE_S:
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case OPC_CMP_NGT_S:
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{
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TCGv_i32 fp0 = tcg_temp_new_i32();
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TCGv_i32 fp1 = tcg_temp_new_i32();
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gen_load_fpr32(fp0, fs);
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gen_load_fpr32(fp1, ft);
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if (ctx->opcode & (1 << 6)) {
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check_cop1x(ctx);
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gen_cmpabs_s(func-48, fp0, fp1, cc);
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opn = condnames_abs[func-48];
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} else {
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gen_cmp_s(func-48, fp0, fp1, cc);
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opn = condnames[func-48];
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}
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tcg_temp_free_i32(fp0);
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tcg_temp_free_i32(fp1);
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if (ctx->opcode & (1 << 6)) {
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gen_cmpabs_s(ctx, func-48, ft, fs, cc);
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opn = condnames_abs[func-48];
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} else {
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gen_cmp_s(ctx, func-48, ft, fs, cc);
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opn = condnames[func-48];
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}
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break;
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case OPC_ADD_D:
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@ -6843,24 +6863,12 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
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case OPC_CMP_NGE_D:
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case OPC_CMP_LE_D:
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case OPC_CMP_NGT_D:
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{
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TCGv_i64 fp0 = tcg_temp_new_i64();
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TCGv_i64 fp1 = tcg_temp_new_i64();
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gen_load_fpr64(ctx, fp0, fs);
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gen_load_fpr64(ctx, fp1, ft);
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if (ctx->opcode & (1 << 6)) {
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check_cop1x(ctx);
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check_cp1_registers(ctx, fs | ft);
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gen_cmpabs_d(func-48, fp0, fp1, cc);
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opn = condnames_abs[func-48];
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} else {
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check_cp1_registers(ctx, fs | ft);
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gen_cmp_d(func-48, fp0, fp1, cc);
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opn = condnames[func-48];
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}
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tcg_temp_free_i64(fp0);
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tcg_temp_free_i64(fp1);
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if (ctx->opcode & (1 << 6)) {
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gen_cmpabs_d(ctx, func-48, ft, fs, cc);
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opn = condnames_abs[func-48];
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} else {
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gen_cmp_d(ctx, func-48, ft, fs, cc);
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opn = condnames[func-48];
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}
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break;
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case OPC_CVT_S_D:
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@ -7280,22 +7288,12 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
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case OPC_CMP_NGE_PS:
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case OPC_CMP_LE_PS:
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case OPC_CMP_NGT_PS:
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check_cp1_64bitmode(ctx);
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{
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TCGv_i64 fp0 = tcg_temp_new_i64();
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TCGv_i64 fp1 = tcg_temp_new_i64();
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gen_load_fpr64(ctx, fp0, fs);
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gen_load_fpr64(ctx, fp1, ft);
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if (ctx->opcode & (1 << 6)) {
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gen_cmpabs_ps(func-48, fp0, fp1, cc);
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opn = condnames_abs[func-48];
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} else {
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gen_cmp_ps(func-48, fp0, fp1, cc);
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opn = condnames[func-48];
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}
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tcg_temp_free_i64(fp0);
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tcg_temp_free_i64(fp1);
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if (ctx->opcode & (1 << 6)) {
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gen_cmpabs_ps(ctx, func-48, ft, fs, cc);
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opn = condnames_abs[func-48];
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} else {
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gen_cmp_ps(ctx, func-48, ft, fs, cc);
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opn = condnames[func-48];
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}
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break;
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default:
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