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target/tricore: Implement ftohp insn
reported in https://gitlab.com/qemu-project/qemu/-/issues/1667 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-ID: <20230828112651.522058-7-kbastian@mail.uni-paderborn.de>
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@ -373,6 +373,44 @@ uint32_t helper_ftoi(CPUTriCoreState *env, uint32_t arg)
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return (uint32_t)result;
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}
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uint32_t helper_ftohp(CPUTriCoreState *env, uint32_t arg)
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{
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float32 f_arg = make_float32(arg);
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uint32_t result = 0;
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int32_t flags = 0;
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/*
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* if we have any NAN we need to move the top 2 and lower 8 input mantissa
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* bits to the top 2 and lower 8 output mantissa bits respectively.
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* Softfloat on the other hand uses the top 10 mantissa bits.
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*/
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if (float32_is_any_nan(f_arg)) {
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if (float32_is_signaling_nan(f_arg, &env->fp_status)) {
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flags |= float_flag_invalid;
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}
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result = float16_set_sign(result, arg >> 31);
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result = deposit32(result, 10, 5, 0x1f);
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result = deposit32(result, 8, 2, extract32(arg, 21, 2));
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result = deposit32(result, 0, 8, extract32(arg, 0, 8));
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if (extract32(result, 0, 10) == 0) {
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result |= (1 << 8);
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}
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} else {
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set_flush_to_zero(0, &env->fp_status);
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result = float32_to_float16(f_arg, true, &env->fp_status);
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set_flush_to_zero(1, &env->fp_status);
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flags = f_get_excp_flags(env);
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}
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if (flags) {
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f_update_psw_flags(env, flags);
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} else {
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env->FPU_FS = 0;
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}
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return result;
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}
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uint32_t helper_itof(CPUTriCoreState *env, uint32_t arg)
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{
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float32 f_result;
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@ -137,6 +137,7 @@ void fpu_set_state(CPUTriCoreState *env)
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set_flush_inputs_to_zero(1, &env->fp_status);
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set_flush_to_zero(1, &env->fp_status);
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set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
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set_default_nan_mode(1, &env->fp_status);
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}
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@ -111,6 +111,7 @@ DEF_HELPER_4(fmsub, i32, env, i32, i32, i32)
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DEF_HELPER_3(fcmp, i32, env, i32, i32)
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DEF_HELPER_2(qseed, i32, env, i32)
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DEF_HELPER_2(ftoi, i32, env, i32)
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DEF_HELPER_2(ftohp, i32, env, i32)
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DEF_HELPER_2(itof, i32, env, i32)
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DEF_HELPER_2(utof, i32, env, i32)
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DEF_HELPER_2(ftoiz, i32, env, i32)
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@ -6260,6 +6260,13 @@ static void decode_rr_divide(DisasContext *ctx)
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case OPC2_32_RR_DIV_F:
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gen_helper_fdiv(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
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break;
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case OPC2_32_RR_FTOHP:
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if (has_feature(ctx, TRICORE_FEATURE_162)) {
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gen_helper_ftohp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
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} else {
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generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
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}
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break;
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case OPC2_32_RR_CMP_F:
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gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
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break;
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@ -1152,6 +1152,7 @@ enum {
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OPC2_32_RR_ITOF = 0x14,
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OPC2_32_RR_CMP_F = 0x00,
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OPC2_32_RR_FTOIZ = 0x13,
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OPC2_32_RR_FTOHP = 0x25, /* 1.6.2 only */
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OPC2_32_RR_FTOQ31 = 0x11,
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OPC2_32_RR_FTOQ31Z = 0x18,
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OPC2_32_RR_FTOU = 0x12,
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@ -14,6 +14,7 @@ TESTS += test_dextr.asm.tst
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TESTS += test_dvstep.asm.tst
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TESTS += test_fadd.asm.tst
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TESTS += test_fmul.asm.tst
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TESTS += test_ftohp.asm.tst
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TESTS += test_ftoi.asm.tst
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TESTS += test_ftou.asm.tst
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TESTS += test_imask.asm.tst
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@ -0,0 +1,14 @@
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#include "macros.h"
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.text
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.global _start
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_start:
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TEST_D_D(ftohp, 1, 0xffff, 0xffffffff)
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TEST_D_D(ftohp, 2, 0xfc00, 0xff800000)
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TEST_D_D(ftohp, 3, 0x7c00, 0x7f800000)
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TEST_D_D(ftohp, 4, 0x0, 0x0)
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TEST_D_D(ftohp, 5, 0x5, 0x34a43580)
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#TEST_D_D_PSW(ftohp, 6, 0x400, 0x8c000b80, 0x387fee74)
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TEST_PASSFAIL
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