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pull-loongarch-20231221 

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Merge tag 'pull-loongarch-20231221' of https://gitlab.com/gaosong/qemu into staging

pull-loongarch-20231221

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# gpg:                using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF
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* tag 'pull-loongarch-20231221' of https://gitlab.com/gaosong/qemu:
  target/loongarch: Add timer information dump support
  hw/loongarch/virt: Align high memory base address with super page size

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2023-12-21 19:44:19 -05:00
parent 6370d13c62 be45144bee
commit 80f1709aa0
2 changed files with 3 additions and 1 deletions
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2
include/hw/loongarch/virt.h
View File

@ -25,7 +25,7 @@
#define VIRT_LOWMEM_BASE 0
#define VIRT_LOWMEM_SIZE 0x10000000
#define VIRT_HIGHMEM_BASE 0x90000000
#define VIRT_HIGHMEM_BASE 0x80000000
#define VIRT_GED_EVT_ADDR 0x100e0000
#define VIRT_GED_MEM_ADDR (VIRT_GED_EVT_ADDR + ACPI_GED_EVT_SEL_LEN)
#define VIRT_GED_REG_ADDR (VIRT_GED_MEM_ADDR + MEMORY_HOTPLUG_IO_LEN)

2
target/loongarch/cpu.c
View File

@ -764,6 +764,8 @@ void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY);
qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV);
qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA);
qemu_fprintf(f, "TCFG=%016" PRIx64 "\n", env->CSR_TCFG);
qemu_fprintf(f, "TVAL=%016" PRIx64 "\n", env->CSR_TVAL);
/* fpr */
if (flags & CPU_DUMP_FPU) {