mirror of https://github.com/xemu-project/xemu.git
hw/net/imx_fec: Convert debug fprintf() to trace events
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [PMD: Fixed 32-bit format string using PRIx32/PRIx64] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Jean-Christophe Dubois
Peter Maydell
parent
9e6f8d8aab
commit
8095508a9d
106
hw/net/imx_fec.c
106
hw/net/imx_fec.c
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@ -31,34 +31,11 @@
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#include "qemu/module.h"
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#include "net/checksum.h"
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#include "net/eth.h"
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#include "trace.h"
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/* For crc32 */
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#include <zlib.h>
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#ifndef DEBUG_IMX_FEC
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#define DEBUG_IMX_FEC 0
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#endif
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#define FEC_PRINTF(fmt, args...) \
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do { \
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if (DEBUG_IMX_FEC) { \
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fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_FEC, \
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__func__, ##args); \
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} \
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} while (0)
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#ifndef DEBUG_IMX_PHY
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#define DEBUG_IMX_PHY 0
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#endif
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#define PHY_PRINTF(fmt, args...) \
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do { \
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if (DEBUG_IMX_PHY) { \
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fprintf(stderr, "[%s.phy]%s: " fmt , TYPE_IMX_FEC, \
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__func__, ##args); \
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} \
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} while (0)
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#define IMX_MAX_DESC 1024
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static const char *imx_default_reg_name(IMXFECState *s, uint32_t index)
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@ -262,43 +239,45 @@ static void imx_eth_update(IMXFECState *s);
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* For now we don't handle any GPIO/interrupt line, so the OS will
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* have to poll for the PHY status.
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*/
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static void phy_update_irq(IMXFECState *s)
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static void imx_phy_update_irq(IMXFECState *s)
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{
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imx_eth_update(s);
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}
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static void phy_update_link(IMXFECState *s)
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static void imx_phy_update_link(IMXFECState *s)
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{
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/* Autonegotiation status mirrors link status. */
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if (qemu_get_queue(s->nic)->link_down) {
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PHY_PRINTF("link is down\n");
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trace_imx_phy_update_link("down");
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s->phy_status &= ~0x0024;
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s->phy_int |= PHY_INT_DOWN;
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} else {
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PHY_PRINTF("link is up\n");
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trace_imx_phy_update_link("up");
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s->phy_status |= 0x0024;
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s->phy_int |= PHY_INT_ENERGYON;
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s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
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}
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phy_update_irq(s);
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imx_phy_update_irq(s);
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}
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static void imx_eth_set_link(NetClientState *nc)
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{
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phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc)));
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imx_phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc)));
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}
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static void phy_reset(IMXFECState *s)
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static void imx_phy_reset(IMXFECState *s)
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{
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trace_imx_phy_reset();
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s->phy_status = 0x7809;
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s->phy_control = 0x3000;
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s->phy_advertise = 0x01e1;
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s->phy_int_mask = 0;
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s->phy_int = 0;
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phy_update_link(s);
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imx_phy_update_link(s);
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}
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static uint32_t do_phy_read(IMXFECState *s, int reg)
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static uint32_t imx_phy_read(IMXFECState *s, int reg)
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{
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uint32_t val;
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@ -332,7 +311,7 @@ static uint32_t do_phy_read(IMXFECState *s, int reg)
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case 29: /* Interrupt source. */
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val = s->phy_int;
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s->phy_int = 0;
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phy_update_irq(s);
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imx_phy_update_irq(s);
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break;
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case 30: /* Interrupt mask */
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val = s->phy_int_mask;
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@ -352,14 +331,14 @@ static uint32_t do_phy_read(IMXFECState *s, int reg)
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break;
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}
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PHY_PRINTF("read 0x%04x @ %d\n", val, reg);
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trace_imx_phy_read(val, reg);
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return val;
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}
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static void do_phy_write(IMXFECState *s, int reg, uint32_t val)
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static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
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{
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PHY_PRINTF("write 0x%04x @ %d\n", val, reg);
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trace_imx_phy_write(val, reg);
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if (reg > 31) {
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/* we only advertise one phy */
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@ -369,7 +348,7 @@ static void do_phy_write(IMXFECState *s, int reg, uint32_t val)
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switch (reg) {
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case 0: /* Basic Control */
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if (val & 0x8000) {
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phy_reset(s);
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imx_phy_reset(s);
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} else {
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s->phy_control = val & 0x7980;
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/* Complete autonegotiation immediately. */
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@ -383,7 +362,7 @@ static void do_phy_write(IMXFECState *s, int reg, uint32_t val)
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break;
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case 30: /* Interrupt mask */
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s->phy_int_mask = val & 0xff;
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phy_update_irq(s);
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imx_phy_update_irq(s);
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break;
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case 17:
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case 18:
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@ -402,6 +381,8 @@ static void do_phy_write(IMXFECState *s, int reg, uint32_t val)
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static void imx_fec_read_bd(IMXFECBufDesc *bd, dma_addr_t addr)
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{
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dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd));
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trace_imx_fec_read_bd(addr, bd->flags, bd->length, bd->data);
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}
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static void imx_fec_write_bd(IMXFECBufDesc *bd, dma_addr_t addr)
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@ -412,6 +393,9 @@ static void imx_fec_write_bd(IMXFECBufDesc *bd, dma_addr_t addr)
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static void imx_enet_read_bd(IMXENETBufDesc *bd, dma_addr_t addr)
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{
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dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd));
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trace_imx_enet_read_bd(addr, bd->flags, bd->length, bd->data,
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bd->option, bd->status);
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}
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static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr)
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@ -471,11 +455,11 @@ static void imx_fec_do_tx(IMXFECState *s)
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int len;
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imx_fec_read_bd(&bd, addr);
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FEC_PRINTF("tx_bd %x flags %04x len %d data %08x\n",
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addr, bd.flags, bd.length, bd.data);
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if ((bd.flags & ENET_BD_R) == 0) {
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/* Run out of descriptors to transmit. */
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FEC_PRINTF("tx_bd ran out of descriptors to transmit\n");
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trace_imx_eth_tx_bd_busy();
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break;
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}
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len = bd.length;
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@ -552,11 +536,11 @@ static void imx_enet_do_tx(IMXFECState *s, uint32_t index)
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int len;
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imx_enet_read_bd(&bd, addr);
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FEC_PRINTF("tx_bd %x flags %04x len %d data %08x option %04x "
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"status %04x\n", addr, bd.flags, bd.length, bd.data,
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bd.option, bd.status);
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if ((bd.flags & ENET_BD_R) == 0) {
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/* Run out of descriptors to transmit. */
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trace_imx_eth_tx_bd_busy();
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break;
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}
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len = bd.length;
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@ -633,7 +617,7 @@ static void imx_eth_enable_rx(IMXFECState *s, bool flush)
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s->regs[ENET_RDAR] = (bd.flags & ENET_BD_E) ? ENET_RDAR_RDAR : 0;
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if (!s->regs[ENET_RDAR]) {
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FEC_PRINTF("RX buffer full\n");
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trace_imx_eth_rx_bd_full();
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} else if (flush) {
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qemu_flush_queued_packets(qemu_get_queue(s->nic));
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}
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@ -676,7 +660,7 @@ static void imx_eth_reset(DeviceState *d)
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memset(s->tx_descriptor, 0, sizeof(s->tx_descriptor));
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/* We also reset the PHY */
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phy_reset(s);
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imx_phy_reset(s);
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}
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static uint32_t imx_default_read(IMXFECState *s, uint32_t index)
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@ -774,8 +758,7 @@ static uint64_t imx_eth_read(void *opaque, hwaddr offset, unsigned size)
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break;
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}
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FEC_PRINTF("reg[%s] => 0x%" PRIx32 "\n", imx_eth_reg_name(s, index),
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value);
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trace_imx_eth_read(index, imx_eth_reg_name(s, index), value);
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return value;
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}
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@ -884,8 +867,7 @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value,
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const bool single_tx_ring = !imx_eth_is_multi_tx_ring(s);
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uint32_t index = offset >> 2;
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FEC_PRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_eth_reg_name(s, index),
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(uint32_t)value);
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trace_imx_eth_write(index, imx_eth_reg_name(s, index), value);
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switch (index) {
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case ENET_EIR:
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@ -940,12 +922,12 @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value,
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if (extract32(value, 29, 1)) {
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/* This is a read operation */
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s->regs[ENET_MMFR] = deposit32(s->regs[ENET_MMFR], 0, 16,
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do_phy_read(s,
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imx_phy_read(s,
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extract32(value,
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18, 10)));
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} else {
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/* This a write operation */
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do_phy_write(s, extract32(value, 18, 10), extract32(value, 0, 16));
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imx_phy_write(s, extract32(value, 18, 10), extract32(value, 0, 16));
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}
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/* raise the interrupt as the PHY operation is done */
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s->regs[ENET_EIR] |= ENET_INT_MII;
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@ -1053,8 +1035,6 @@ static bool imx_eth_can_receive(NetClientState *nc)
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{
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IMXFECState *s = IMX_FEC(qemu_get_nic_opaque(nc));
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FEC_PRINTF("\n");
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return !!s->regs[ENET_RDAR];
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}
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@ -1071,7 +1051,7 @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf,
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unsigned int buf_len;
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size_t size = len;
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FEC_PRINTF("len %d\n", (int)size);
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trace_imx_fec_receive(size);
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if (!s->regs[ENET_RDAR]) {
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Unexpected packet\n",
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@ -1113,7 +1093,7 @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf,
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bd.length = buf_len;
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size -= buf_len;
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FEC_PRINTF("rx_bd 0x%x length %d\n", addr, bd.length);
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trace_imx_fec_receive_len(addr, bd.length);
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/* The last 4 bytes are the CRC. */
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if (size < 4) {
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@ -1131,7 +1111,9 @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf,
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if (size == 0) {
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/* Last buffer in frame. */
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bd.flags |= flags | ENET_BD_L;
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FEC_PRINTF("rx frame flags %04x\n", bd.flags);
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trace_imx_fec_receive_last(bd.flags);
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s->regs[ENET_EIR] |= ENET_INT_RXF;
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} else {
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s->regs[ENET_EIR] |= ENET_INT_RXB;
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@ -1164,7 +1146,7 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf,
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size_t size = len;
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bool shift16 = s->regs[ENET_RACC] & ENET_RACC_SHIFT16;
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FEC_PRINTF("len %d\n", (int)size);
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trace_imx_enet_receive(size);
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if (!s->regs[ENET_RDAR]) {
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Unexpected packet\n",
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@ -1210,7 +1192,7 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf,
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bd.length = buf_len;
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size -= buf_len;
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FEC_PRINTF("rx_bd 0x%x length %d\n", addr, bd.length);
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trace_imx_enet_receive_len(addr, bd.length);
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/* The last 4 bytes are the CRC. */
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if (size < 4) {
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@ -1246,7 +1228,9 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf,
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if (size == 0) {
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/* Last buffer in frame. */
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bd.flags |= flags | ENET_BD_L;
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FEC_PRINTF("rx frame flags %04x\n", bd.flags);
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trace_imx_enet_receive_last(bd.flags);
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/* Indicate that we've updated the last buffer descriptor. */
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bd.last_buffer = ENET_BD_BDU;
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if (bd.option & ENET_BD_RX_INT) {
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@ -408,3 +408,21 @@ i82596_receive_packet(size_t sz) "len=%zu"
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i82596_new_mac(const char *id_with_mac) "New MAC for: %s"
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i82596_set_multicast(uint16_t count) "Added %d multicast entries"
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i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION"
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# imx_fec.c
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imx_phy_read(uint32_t val, int reg) "0x%04"PRIx32" <= reg[%d]"
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imx_phy_write(uint32_t val, int reg) "0x%04"PRIx32" => reg[%d]"
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imx_phy_update_link(const char *s) "%s"
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imx_phy_reset(void) ""
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imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x"
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imx_enet_read_bd(uint64_t addr, int flags, int len, int data, int options, int status) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x option 0x%04x status 0x%04x"
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imx_eth_tx_bd_busy(void) "tx_bd ran out of descriptors to transmit"
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imx_eth_rx_bd_full(void) "RX buffer is full"
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imx_eth_read(int reg, const char *reg_name, uint32_t value) "reg[%d:%s] => 0x%08"PRIx32
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imx_eth_write(int reg, const char *reg_name, uint64_t value) "reg[%d:%s] <= 0x%08"PRIx64
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imx_fec_receive(size_t size) "len %zu"
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imx_fec_receive_len(uint64_t addr, int len) "rx_bd 0x%"PRIx64" length %d"
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imx_fec_receive_last(int last) "rx frame flags 0x%04x"
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imx_enet_receive(size_t size) "len %zu"
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imx_enet_receive_len(uint64_t addr, int len) "rx_bd 0x%"PRIx64" length %d"
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imx_enet_receive_last(int last) "rx frame flags 0x%04x"
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