mirror of https://github.com/xemu-project/xemu.git
target-sparc: Use overalignment flags for twinx and block asis
This allows us to enforce 16 and 64-byte alignment without any extra overhead. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1466744068-6615-1-git-send-email-rth@twiddle.net>
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@ -2385,20 +2385,23 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr,
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case GET_ASI_BLOCK:
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/* Valid for lddfa on aligned registers only. */
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if (size == 8 && (rd & 7) == 0) {
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TCGMemOp memop;
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TCGv eight;
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int i;
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gen_check_align(addr, 0x3f);
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gen_address_mask(dc, addr);
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/* The first operation checks required alignment. */
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memop = da.memop | MO_ALIGN_64;
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eight = tcg_const_tl(8);
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for (i = 0; ; ++i) {
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tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr,
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da.mem_idx, da.memop);
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da.mem_idx, memop);
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if (i == 7) {
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break;
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}
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tcg_gen_add_tl(addr, addr, eight);
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memop = da.memop;
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}
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tcg_temp_free(eight);
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} else {
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@ -2488,20 +2491,23 @@ static void gen_stf_asi(DisasContext *dc, TCGv addr,
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case GET_ASI_BLOCK:
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/* Valid for stdfa on aligned registers only. */
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if (size == 8 && (rd & 7) == 0) {
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TCGMemOp memop;
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TCGv eight;
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int i;
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gen_check_align(addr, 0x3f);
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gen_address_mask(dc, addr);
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/* The first operation checks required alignment. */
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memop = da.memop | MO_ALIGN_64;
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eight = tcg_const_tl(8);
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for (i = 0; ; ++i) {
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tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr,
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da.mem_idx, da.memop);
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da.mem_idx, memop);
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if (i == 7) {
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break;
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}
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tcg_gen_add_tl(addr, addr, eight);
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memop = da.memop;
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}
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tcg_temp_free(eight);
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} else {
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@ -2539,9 +2545,8 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
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return;
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case GET_ASI_DTWINX:
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gen_check_align(addr, 15);
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gen_address_mask(dc, addr);
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tcg_gen_qemu_ld_i64(hi, addr, da.mem_idx, da.memop);
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tcg_gen_qemu_ld_i64(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
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tcg_gen_addi_tl(addr, addr, 8);
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tcg_gen_qemu_ld_i64(lo, addr, da.mem_idx, da.memop);
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break;
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@ -2594,9 +2599,8 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
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break;
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case GET_ASI_DTWINX:
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gen_check_align(addr, 15);
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gen_address_mask(dc, addr);
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tcg_gen_qemu_st_i64(hi, addr, da.mem_idx, da.memop);
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tcg_gen_qemu_st_i64(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
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tcg_gen_addi_tl(addr, addr, 8);
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tcg_gen_qemu_st_i64(lo, addr, da.mem_idx, da.memop);
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break;
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@ -5468,7 +5472,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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if (gen_trap_ifnofpu(dc)) {
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goto jmp_insn;
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}
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gen_check_align(cpu_addr, 7);
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gen_stf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));
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}
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break;
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