mirror of https://github.com/xemu-project/xemu.git
nvnet: Fix checkpatch nits
This commit is contained in:
Matt Borgerson
Jannik Vogel
parent
f63c322740
commit
8075a2f7ce
112
hw/xbox/nvnet.c
112
hw/xbox/nvnet.c
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@ -63,8 +63,8 @@ enum {
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# define NVREG_IRQ_TX1 0x0100
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# define NVREG_IRQMASK_WANTED_1 0x005f
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# define NVREG_IRQMASK_WANTED_2 0x0147
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# define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|\
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NVREG_IRQ_TX_ERR|NVREG_IRQ_TX2|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|\
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# define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX | NVREG_IRQ_RX_NOBUF | \
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NVREG_IRQ_TX_ERR | NVREG_IRQ_TX2 | NVREG_IRQ_TIMER | NVREG_IRQ_LINK | \
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NVREG_IRQ_TX1))
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NvRegUnknownSetupReg6 = 0x008,
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# define NVREG_UNKSETUP6_VAL 3
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@ -118,7 +118,7 @@ enum {
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# define NVREG_LINKSPEED_100 100
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# define NVREG_LINKSPEED_1000 1000
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NvRegUnknownSetupReg5 = 0x130,
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# define NVREG_UNKSETUP5_BIT31 (1<<31)
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# define NVREG_UNKSETUP5_BIT31 (1 << 31)
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NvRegUnknownSetupReg3 = 0x134,
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# define NVREG_UNKSETUP3_VAL1 0x200010
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NvRegUnknownSetupReg8 = 0x13C,
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@ -145,7 +145,7 @@ enum {
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# define NVREG_ADAPTCTL_RUNNING 0x100000
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# define NVREG_ADAPTCTL_PHYSHIFT 24
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NvRegMIISpeed = 0x18c,
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# define NVREG_MIISPEED_BIT8 (1<<8)
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# define NVREG_MIISPEED_BIT8 (1 << 8)
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# define NVREG_MIIDELAY 5
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NvRegMIIControl = 0x190,
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# define NVREG_MIICTL_INUSE 0x10000
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@ -166,9 +166,9 @@ enum {
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NvRegPatternCRC = 0x204,
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NvRegPatternMask = 0x208,
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NvRegPowerCap = 0x268,
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# define NVREG_POWERCAP_D3SUPP (1<<30)
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# define NVREG_POWERCAP_D2SUPP (1<<26)
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# define NVREG_POWERCAP_D1SUPP (1<<25)
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# define NVREG_POWERCAP_D3SUPP (1 << 30)
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# define NVREG_POWERCAP_D2SUPP (1 << 26)
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# define NVREG_POWERCAP_D1SUPP (1 << 25)
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NvRegPowerState = 0x26c,
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# define NVREG_POWERSTATE_POWEREDUP 0x8000
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# define NVREG_POWERSTATE_VALID 0x0100
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@ -179,28 +179,28 @@ enum {
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# define NVREG_POWERSTATE_D3 0x0003
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};
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#define NV_TX_LASTPACKET (1<<0)
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#define NV_TX_RETRYERROR (1<<3)
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#define NV_TX_LASTPACKET1 (1<<8)
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#define NV_TX_DEFERRED (1<<10)
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#define NV_TX_CARRIERLOST (1<<11)
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#define NV_TX_LATECOLLISION (1<<12)
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#define NV_TX_UNDERFLOW (1<<13)
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#define NV_TX_ERROR (1<<14)
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#define NV_TX_VALID (1<<15)
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#define NV_RX_DESCRIPTORVALID (1<<0)
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#define NV_RX_MISSEDFRAME (1<<1)
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#define NV_RX_SUBSTRACT1 (1<<3)
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#define NV_RX_BIT4 (1<<4)
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#define NV_RX_ERROR1 (1<<7)
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#define NV_RX_ERROR2 (1<<8)
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#define NV_RX_ERROR3 (1<<9)
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#define NV_RX_ERROR4 (1<<10)
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#define NV_RX_CRCERR (1<<11)
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#define NV_RX_OVERFLOW (1<<12)
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#define NV_RX_FRAMINGERR (1<<13)
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#define NV_RX_ERROR (1<<14)
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#define NV_RX_AVAIL (1<<15)
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#define NV_TX_LASTPACKET (1 << 0)
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#define NV_TX_RETRYERROR (1 << 3)
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#define NV_TX_LASTPACKET1 (1 << 8)
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#define NV_TX_DEFERRED (1 << 10)
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#define NV_TX_CARRIERLOST (1 << 11)
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#define NV_TX_LATECOLLISION (1 << 12)
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#define NV_TX_UNDERFLOW (1 << 13)
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#define NV_TX_ERROR (1 << 14)
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#define NV_TX_VALID (1 << 15)
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#define NV_RX_DESCRIPTORVALID (1 << 0)
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#define NV_RX_MISSEDFRAME (1 << 1)
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#define NV_RX_SUBSTRACT1 (1 << 3)
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#define NV_RX_BIT4 (1 << 4)
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#define NV_RX_ERROR1 (1 << 7)
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#define NV_RX_ERROR2 (1 << 8)
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#define NV_RX_ERROR3 (1 << 9)
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#define NV_RX_ERROR4 (1 << 10)
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#define NV_RX_CRCERR (1 << 11)
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#define NV_RX_OVERFLOW (1 << 12)
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#define NV_RX_FRAMINGERR (1 << 13)
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#define NV_RX_ERROR (1 << 14)
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#define NV_RX_AVAIL (1 << 15)
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/* Miscelaneous hardware related defines: */
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#define NV_PCI_REGSZ 0x270
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@ -224,7 +224,7 @@ enum {
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#define NV_WAKEUPMASKENTRIES 4
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/* General driver defaults */
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#define NV_WATCHDOG_TIMEO (2*HZ)
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#define NV_WATCHDOG_TIMEO (2 * HZ)
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#define DEFAULT_MTU 1500
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#define RX_RING 4
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@ -233,13 +233,13 @@ enum {
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#define TX_LIMIT_STOP 10
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#define TX_LIMIT_START 5
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/* rx/tx mac addr + type + vlan + align + slack*/
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/* rx / tx mac addr + type + vlan + align + slack*/
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#define RX_NIC_BUFSIZE (DEFAULT_MTU + 64)
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/* even more slack */
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#define RX_ALLOC_BUFSIZE (DEFAULT_MTU + 128)
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#define OOM_REFILL (1+HZ/20)
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#define POLL_WAIT (1+HZ/100)
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#define OOM_REFILL (1 + HZ / 20)
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#define POLL_WAIT (1 + HZ / 100)
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#define MII_READ (-1)
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#define MII_PHYSID1 0x02 /* PHYS ID 1 */
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@ -273,7 +273,7 @@ typedef struct NvNetState {
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NICState *nic;
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NICConf conf;
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MemoryRegion mmio, io;
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uint8_t regs[MMIO_SIZE/4];
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uint8_t regs[MMIO_SIZE / 4];
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uint32_t phy_regs[6];
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uint8_t tx_ring_index;
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uint8_t tx_ring_size;
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@ -334,7 +334,7 @@ static void nvnet_set_link_status(NetClientState *nc);
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/* Interrupts */
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static void nvnet_update_irq(NvNetState *s);
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/* Packet Tx/Rx */
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/* Packet Tx / Rx */
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static void nvnet_send_packet(NvNetState *s,
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const uint8_t *buf, int size);
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static ssize_t nvnet_dma_packet_to_guest(NvNetState *s,
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@ -384,11 +384,11 @@ static uint32_t nvnet_get_reg(NvNetState *s, hwaddr addr, unsigned int size)
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switch (size) {
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case 4:
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assert((addr & 3) == 0); /* Unaligned register access. */
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return ((uint32_t *)s->regs)[addr>>2];
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return ((uint32_t *)s->regs)[addr >> 2];
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case 2:
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assert((addr & 1) == 0); /* Unaligned register access. */
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return ((uint16_t *)s->regs)[addr>>1];
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return ((uint16_t *)s->regs)[addr >> 1];
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case 1:
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return s->regs[addr];
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@ -407,12 +407,12 @@ static void nvnet_set_reg(NvNetState *s,
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switch (size) {
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case 4:
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assert((addr & 3) == 0); /* Unaligned register access. */
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((uint32_t *)s->regs)[addr>>2] = val;
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((uint32_t *)s->regs)[addr >> 2] = val;
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break;
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case 2:
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assert((addr & 1) == 0); /* Unaligned register access. */
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((uint16_t *)s->regs)[addr>>1] = (uint16_t)val;
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((uint16_t *)s->regs)[addr >> 1] = (uint16_t)val;
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break;
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case 1:
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@ -476,7 +476,7 @@ static int nvnet_mii_rw(NvNetState *s, uint64_t val)
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}
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/*******************************************************************************
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* MMIO Read/Write
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* MMIO Read / Write
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******************************************************************************/
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/*
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@ -532,8 +532,8 @@ static void nvnet_mmio_write(void *opaque, hwaddr addr,
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switch (addr) {
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case NvRegRingSizes:
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nvnet_set_reg(s, addr, val, size);
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s->rx_ring_size = ((val >> NVREG_RINGSZ_RXSHIFT) & 0xffff)+1;
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s->tx_ring_size = ((val >> NVREG_RINGSZ_TXSHIFT) & 0xffff)+1;
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s->rx_ring_size = ((val >> NVREG_RINGSZ_RXSHIFT) & 0xffff) + 1;
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s->tx_ring_size = ((val >> NVREG_RINGSZ_TXSHIFT) & 0xffff) + 1;
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break;
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case NvRegMIIData:
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@ -589,7 +589,7 @@ static const MemoryRegionOps nvnet_mmio_ops = {
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};
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/*******************************************************************************
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* Packet TX/RX
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* Packet TX / RX
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******************************************************************************/
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static void nvnet_send_packet(NvNetState *s, const uint8_t *buf, int size)
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@ -648,7 +648,7 @@ static ssize_t nvnet_dma_packet_to_guest(NvNetState *s,
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/* Read current ring descriptor */
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s->rx_ring_index %= s->rx_ring_size;
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dma_addr_t rx_ring_addr = nvnet_get_reg(s, NvRegRxRingPhysAddr, 4);
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rx_ring_addr += s->rx_ring_index*sizeof(desc);
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rx_ring_addr += s->rx_ring_index * sizeof(desc);
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pci_dma_read(&s->dev, rx_ring_addr, &desc, sizeof(desc));
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NVNET_DPRINTF("Looking at ring descriptor %d (0x%llx): ",
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s->rx_ring_index, rx_ring_addr);
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@ -714,15 +714,15 @@ static ssize_t nvnet_dma_packet_from_guest(NvNetState *s)
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/* Transfer packet from guest memory */
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NVNET_DPRINTF("Sending packet...\n");
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pci_dma_read(&s->dev, desc.packet_buffer,
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s->txrx_dma_buf, desc.length+1);
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nvnet_send_packet(s, s->txrx_dma_buf, desc.length+1);
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s->txrx_dma_buf, desc.length + 1);
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nvnet_send_packet(s, s->txrx_dma_buf, desc.length + 1);
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/* Update descriptor */
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is_last_packet = desc.flags & NV_TX_LASTPACKET;
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desc.flags &= ~(NV_TX_VALID | NV_TX_RETRYERROR | NV_TX_DEFERRED |
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NV_TX_CARRIERLOST | NV_TX_LATECOLLISION | NV_TX_UNDERFLOW |
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NV_TX_ERROR);
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desc.length = desc.length+5;
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desc.length = desc.length + 5;
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pci_dma_write(&s->dev, tx_ring_addr, &desc, sizeof(desc));
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if (is_last_packet) {
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@ -764,7 +764,7 @@ static void nvnet_set_link_status(NetClientState *nc)
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}
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/*******************************************************************************
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* IO Read/Write
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* IO Read / Write
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******************************************************************************/
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static uint64_t nvnet_io_read(void *opaque, hwaddr addr, unsigned int size)
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@ -825,12 +825,12 @@ static void nvnet_realize(PCIDevice *pci_dev, Error **errp)
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object_get_typename(OBJECT(s)), dev->id, s);
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assert(s->nic);
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s->regs[NvRegMacAddrA+0x00] = s->conf.macaddr.a[0];
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s->regs[NvRegMacAddrA+0x01] = s->conf.macaddr.a[1];
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s->regs[NvRegMacAddrA+0x02] = s->conf.macaddr.a[2];
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s->regs[NvRegMacAddrA+0x03] = s->conf.macaddr.a[3];
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s->regs[NvRegMacAddrB+0x00] = s->conf.macaddr.a[4];
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s->regs[NvRegMacAddrB+0x01] = s->conf.macaddr.a[5];
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s->regs[NvRegMacAddrA + 0x00] = s->conf.macaddr.a[0];
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s->regs[NvRegMacAddrA + 0x01] = s->conf.macaddr.a[1];
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s->regs[NvRegMacAddrA + 0x02] = s->conf.macaddr.a[2];
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s->regs[NvRegMacAddrA + 0x03] = s->conf.macaddr.a[3];
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s->regs[NvRegMacAddrB + 0x00] = s->conf.macaddr.a[4];
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s->regs[NvRegMacAddrB + 0x01] = s->conf.macaddr.a[5];
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}
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static void nvnet_uninit(PCIDevice *dev)
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@ -881,14 +881,14 @@ static void hex_dump(FILE *f, const uint8_t *buf, int size)
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fprintf(f, "%08x ", i);
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for (j = 0; j < 16; j++) {
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if (j < len) {
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fprintf(f, " %02x", buf[i+j]);
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fprintf(f, " %02x", buf[i + j]);
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} else {
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fprintf(f, " ");
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}
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}
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fprintf(f, " ");
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for (j = 0; j < len; j++) {
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c = buf[i+j];
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c = buf[i + j];
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if (c < ' ' || c > '~') {
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c = '.';
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}
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