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target-mips: Correct the handling of register #72 on writes
Fix an off-by-one error in `mips_cpu_gdb_write_register' for register matching how `mips_cpu_gdb_read_register' handles it. This register slot is a fake anyway, there's nothing in hardware that corresponds to it. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
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@ -90,7 +90,7 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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return sizeof(target_ulong);
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}
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if (env->CP0_Config1 & (1 << CP0C1_FP)
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&& n >= 38 && n < 73) {
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&& n >= 38 && n < 72) {
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if (n < 70) {
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if (env->CP0_Status & (1 << CP0St_FR)) {
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env->active_fpu.fpr[n - 38].d = tmp;
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