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target/arm: Add isar_feature_aa32_vfp_simd 

Use this in the places that were checking ARM_FEATURE_VFP, and
are obviously testing for the existance of the register set
as opposed to testing for some particular instruction extension.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200224222232.13807-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2020-02-24 14:22:16 -08:00 committed by Peter Maydell
parent 25f1d9f38b
commit 7fbc6a403a
7 changed files with 37 additions and 26 deletions
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20
hw/intc/armv7m_nvic.c
View File

@ -1262,12 +1262,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
case 0xd84: /* CSSELR */ case 0xd84: /* CSSELR */
return cpu->env.v7m.csselr[attrs.secure]; return cpu->env.v7m.csselr[attrs.secure];
case 0xd88: /* CPACR */ case 0xd88: /* CPACR */
if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
return 0; return 0;
} }
return cpu->env.v7m.cpacr[attrs.secure]; return cpu->env.v7m.cpacr[attrs.secure];
case 0xd8c: /* NSACR */ case 0xd8c: /* NSACR */
if (!attrs.secure || !arm_feature(&cpu->env, ARM_FEATURE_VFP)) { if (!attrs.secure || !cpu_isar_feature(aa32_vfp_simd, cpu)) {
return 0; return 0;
} }
return cpu->env.v7m.nsacr; return cpu->env.v7m.nsacr;
@ -1417,7 +1417,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
} }
return cpu->env.v7m.sfar; return cpu->env.v7m.sfar;
case 0xf34: /* FPCCR */ case 0xf34: /* FPCCR */
if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
return 0; return 0;
} }
if (attrs.secure) { if (attrs.secure) {
@ -1444,12 +1444,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
return value; return value;
} }
case 0xf38: /* FPCAR */ case 0xf38: /* FPCAR */
if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
return 0; return 0;
} }
return cpu->env.v7m.fpcar[attrs.secure]; return cpu->env.v7m.fpcar[attrs.secure];
case 0xf3c: /* FPDSCR */ case 0xf3c: /* FPDSCR */
if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
return 0; return 0;
} }
return cpu->env.v7m.fpdscr[attrs.secure]; return cpu->env.v7m.fpdscr[attrs.secure];
@ -1711,13 +1711,13 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
} }
break; break;
case 0xd88: /* CPACR */ case 0xd88: /* CPACR */
if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
/* We implement only the Floating Point extension's CP10/CP11 */ /* We implement only the Floating Point extension's CP10/CP11 */
cpu->env.v7m.cpacr[attrs.secure] = value & (0xf << 20); cpu->env.v7m.cpacr[attrs.secure] = value & (0xf << 20);
} }
break; break;
case 0xd8c: /* NSACR */ case 0xd8c: /* NSACR */
if (attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_VFP)) { if (attrs.secure && cpu_isar_feature(aa32_vfp_simd, cpu)) {
/* We implement only the Floating Point extension's CP10/CP11 */ /* We implement only the Floating Point extension's CP10/CP11 */
cpu->env.v7m.nsacr = value & (3 << 10); cpu->env.v7m.nsacr = value & (3 << 10);
} }
@ -1951,7 +1951,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
break; break;
} }
case 0xf34: /* FPCCR */ case 0xf34: /* FPCCR */
if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
/* Not all bits here are banked. */ /* Not all bits here are banked. */
uint32_t fpccr_s; uint32_t fpccr_s;
@ -2005,13 +2005,13 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
} }
break; break;
case 0xf38: /* FPCAR */ case 0xf38: /* FPCAR */
if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
value &= ~7; value &= ~7;
cpu->env.v7m.fpcar[attrs.secure] = value; cpu->env.v7m.fpcar[attrs.secure] = value;
} }
break; break;
case 0xf3c: /* FPDSCR */ case 0xf3c: /* FPDSCR */
if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
value &= 0x07c00000; value &= 0x07c00000;
cpu->env.v7m.fpdscr[attrs.secure] = value; cpu->env.v7m.fpdscr[attrs.secure] = value;
} }

4
linux-user/arm/signal.c
View File

@ -346,7 +346,7 @@ static void setup_sigframe_v2(struct target_ucontext_v2 *uc,
setup_sigcontext(&uc->tuc_mcontext, env, set->sig[0]); setup_sigcontext(&uc->tuc_mcontext, env, set->sig[0]);
/* Save coprocessor signal frame. */ /* Save coprocessor signal frame. */
regspace = uc->tuc_regspace; regspace = uc->tuc_regspace;
if (arm_feature(env, ARM_FEATURE_VFP)) { if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {
regspace = setup_sigframe_v2_vfp(regspace, env); regspace = setup_sigframe_v2_vfp(regspace, env);
} }
if (arm_feature(env, ARM_FEATURE_IWMMXT)) { if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
@ -671,7 +671,7 @@ static int do_sigframe_return_v2(CPUARMState *env,
/* Restore coprocessor signal frame */ /* Restore coprocessor signal frame */
regspace = uc->tuc_regspace; regspace = uc->tuc_regspace;
if (arm_feature(env, ARM_FEATURE_VFP)) { if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {
regspace = restore_sigframe_v2_vfp(env, regspace); regspace = restore_sigframe_v2_vfp(env, regspace);
if (!regspace) { if (!regspace) {
return 1; return 1;

11
target/arm/arch_dump.c
View File

@ -363,9 +363,11 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, void *opaque) int cpuid, void *opaque)
{ {
struct arm_note note; struct arm_note note;
CPUARMState *env = &ARM_CPU(cs)->env; ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
DumpState *s = opaque; DumpState *s = opaque;
int ret, i, fpvalid = !!arm_feature(env, ARM_FEATURE_VFP); int ret, i;
bool fpvalid = cpu_isar_feature(aa32_vfp_simd, cpu);
arm_note_init(&note, s, "CORE", 5, NT_PRSTATUS, sizeof(note.prstatus)); arm_note_init(&note, s, "CORE", 5, NT_PRSTATUS, sizeof(note.prstatus));
@ -444,7 +446,6 @@ int cpu_get_dump_info(ArchDumpInfo *info,
ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)
{ {
ARMCPU *cpu = ARM_CPU(first_cpu); ARMCPU *cpu = ARM_CPU(first_cpu);
CPUARMState *env = &cpu->env;
size_t note_size; size_t note_size;
if (class == ELFCLASS64) { if (class == ELFCLASS64) {
@ -452,12 +453,12 @@ ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)
note_size += AARCH64_PRFPREG_NOTE_SIZE; note_size += AARCH64_PRFPREG_NOTE_SIZE;
#ifdef TARGET_AARCH64 #ifdef TARGET_AARCH64
if (cpu_isar_feature(aa64_sve, cpu)) { if (cpu_isar_feature(aa64_sve, cpu)) {
note_size += AARCH64_SVE_NOTE_SIZE(env); note_size += AARCH64_SVE_NOTE_SIZE(&cpu->env);
} }
#endif #endif
} else { } else {
note_size = ARM_PRSTATUS_NOTE_SIZE; note_size = ARM_PRSTATUS_NOTE_SIZE;
if (arm_feature(env, ARM_FEATURE_VFP)) { if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
note_size += ARM_VFP_NOTE_SIZE; note_size += ARM_VFP_NOTE_SIZE;
} }
} }

4
target/arm/cpu.c
View File

@ -293,7 +293,7 @@ static void arm_cpu_reset(CPUState *s)
env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;
} }
if (arm_feature(env, ARM_FEATURE_VFP)) { if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK;
env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK |
R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK;
@ -1011,7 +1011,7 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
int numvfpregs = 0; int numvfpregs = 0;
if (cpu_isar_feature(aa32_simd_r32, cpu)) { if (cpu_isar_feature(aa32_simd_r32, cpu)) {
numvfpregs = 32; numvfpregs = 32;
} else if (arm_feature(env, ARM_FEATURE_VFP)) { } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
numvfpregs = 16; numvfpregs = 16;
} }
for (i = 0; i < numvfpregs; i++) { for (i = 0; i < numvfpregs; i++) {

9
target/arm/cpu.h
View File

@ -3450,6 +3450,15 @@ static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
} }
static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
{
/*
* Return true if either VFP or SIMD is implemented.
* In this case, a minimum of VFP w/ D0-D15.
*/
return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0;
}
static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id)
{ {
/* Return true if D16-D31 are implemented */ /* Return true if D16-D31 are implemented */

4
target/arm/helper.c
View File

@ -894,7 +894,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
* ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
* TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell. * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
*/ */
if (arm_feature(env, ARM_FEATURE_VFP)) { if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {
/* VFP coprocessor: cp10 & cp11 [23:20] */ /* VFP coprocessor: cp10 & cp11 [23:20] */
mask |= (1 << 31) | (1 << 30) | (0xf << 20); mask |= (1 << 31) | (1 << 30) | (0xf << 20);
@ -7814,7 +7814,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
} else if (cpu_isar_feature(aa32_simd_r32, cpu)) { } else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
35, "arm-vfp3.xml", 0); 35, "arm-vfp3.xml", 0);
} else if (arm_feature(env, ARM_FEATURE_VFP)) { } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
19, "arm-vfp.xml", 0); 19, "arm-vfp.xml", 0);
} }

11
target/arm/m_helper.c
View File

@ -738,7 +738,8 @@ static uint32_t v7m_integrity_sig(CPUARMState *env, uint32_t lr)
*/ */
uint32_t sig = 0xfefa125a; uint32_t sig = 0xfefa125a;
if (!arm_feature(env, ARM_FEATURE_VFP) || (lr & R_V7M_EXCRET_FTYPE_MASK)) { if (!cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))
|| (lr & R_V7M_EXCRET_FTYPE_MASK)) {
sig |= 1; sig |= 1;
} }
return sig; return sig;
@ -841,7 +842,7 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
if (dotailchain) { if (dotailchain) {
/* Sanitize LR FType and PREFIX bits */ /* Sanitize LR FType and PREFIX bits */
if (!arm_feature(env, ARM_FEATURE_VFP)) { if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
lr |= R_V7M_EXCRET_FTYPE_MASK; lr |= R_V7M_EXCRET_FTYPE_MASK;
} }
lr = deposit32(lr, 24, 8, 0xff); lr = deposit32(lr, 24, 8, 0xff);
@ -1373,7 +1374,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
ftype = excret & R_V7M_EXCRET_FTYPE_MASK; ftype = excret & R_V7M_EXCRET_FTYPE_MASK;
if (!arm_feature(env, ARM_FEATURE_VFP) && !ftype) { if (!ftype && !cpu_isar_feature(aa32_vfp_simd, cpu)) {
qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero FTYPE in exception " qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero FTYPE in exception "
"exit PC value 0x%" PRIx32 " is UNPREDICTABLE " "exit PC value 0x%" PRIx32 " is UNPREDICTABLE "
"if FPU not present\n", "if FPU not present\n",
@ -2450,7 +2451,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
* SFPA is RAZ/WI from NS. FPCA is RO if NSACR.CP10 == 0, * SFPA is RAZ/WI from NS. FPCA is RO if NSACR.CP10 == 0,
* RES0 if the FPU is not present, and is stored in the S bank * RES0 if the FPU is not present, and is stored in the S bank
*/ */
if (arm_feature(env, ARM_FEATURE_VFP) && if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env)) &&
extract32(env->v7m.nsacr, 10, 1)) { extract32(env->v7m.nsacr, 10, 1)) {
env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_FPCA_MASK; env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_FPCA_MASK;
env->v7m.control[M_REG_S] |= val & R_V7M_CONTROL_FPCA_MASK; env->v7m.control[M_REG_S] |= val & R_V7M_CONTROL_FPCA_MASK;
@ -2565,7 +2566,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK; env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK;
env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK; env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK;
} }
if (arm_feature(env, ARM_FEATURE_VFP)) { if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {
/* /*
* SFPA is RAZ/WI from NS or if no FPU. * SFPA is RAZ/WI from NS or if no FPU.
* FPCA is RO if NSACR.CP10 == 0, RES0 if the FPU is not present. * FPCA is RO if NSACR.CP10 == 0, RES0 if the FPU is not present.