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target/ppc: Add helper for fmuls 

Use float64r32_mul.  Fixes a double-rounding issue with performing
the compuation in float64 and then rounding afterward.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-32-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Richard Henderson 2021-12-17 17:57:16 +01:00 committed by Cédric Le Goater
parent d9e792a1c1
commit 7f87214e3b
3 changed files with 17 additions and 7 deletions
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12
target/ppc/fpu_helper.c
View File

@ -581,6 +581,18 @@ float64 helper_fmul(CPUPPCState *env, float64 arg1, float64 arg2)
return ret; return ret;
} }
/* fmuls - fmuls. */
float64 helper_fmuls(CPUPPCState *env, float64 arg1, float64 arg2)
{
float64 ret = float64r32_mul(arg1, arg2, &env->fp_status);
int flags = get_float_exception_flags(&env->fp_status);
if (unlikely(flags & float_flag_invalid)) {
float_invalid_op_mul(env, flags, 1, GETPC());
}
return ret;
}
static void float_invalid_op_div(CPUPPCState *env, int flags, static void float_invalid_op_div(CPUPPCState *env, int flags,
bool set_fprc, uintptr_t retaddr) bool set_fprc, uintptr_t retaddr)
{ {

1
target/ppc/helper.h
View File

@ -98,6 +98,7 @@ DEF_HELPER_3(fadds, f64, env, f64, f64)
DEF_HELPER_3(fsub, f64, env, f64, f64) DEF_HELPER_3(fsub, f64, env, f64, f64)
DEF_HELPER_3(fsubs, f64, env, f64, f64) DEF_HELPER_3(fsubs, f64, env, f64, f64)
DEF_HELPER_3(fmul, f64, env, f64, f64) DEF_HELPER_3(fmul, f64, env, f64, f64)
DEF_HELPER_3(fmuls, f64, env, f64, f64)
DEF_HELPER_3(fdiv, f64, env, f64, f64) DEF_HELPER_3(fdiv, f64, env, f64, f64)
DEF_HELPER_3(fdivs, f64, env, f64, f64) DEF_HELPER_3(fdivs, f64, env, f64, f64)
DEF_HELPER_4(fmadd, i64, env, i64, i64, i64) DEF_HELPER_4(fmadd, i64, env, i64, i64, i64)

11
target/ppc/translate/fp-impl.c.inc
View File

@ -100,7 +100,7 @@ static void gen_f##name(DisasContext *ctx) \
_GEN_FLOAT_AB(name, 0x3F, op2, inval, set_fprf, type); \ _GEN_FLOAT_AB(name, 0x3F, op2, inval, set_fprf, type); \
_GEN_FLOAT_AB(name##s, 0x3B, op2, inval, set_fprf, type); _GEN_FLOAT_AB(name##s, 0x3B, op2, inval, set_fprf, type);
#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ #define _GEN_FLOAT_AC(name, op1, op2, inval, set_fprf, type) \
static void gen_f##name(DisasContext *ctx) \ static void gen_f##name(DisasContext *ctx) \
{ \ { \
TCGv_i64 t0; \ TCGv_i64 t0; \
@ -116,10 +116,7 @@ static void gen_f##name(DisasContext *ctx) \
gen_reset_fpstatus(); \ gen_reset_fpstatus(); \
get_fpr(t0, rA(ctx->opcode)); \ get_fpr(t0, rA(ctx->opcode)); \
get_fpr(t1, rC(ctx->opcode)); \ get_fpr(t1, rC(ctx->opcode)); \
gen_helper_f##op(t2, cpu_env, t0, t1); \ gen_helper_f##name(t2, cpu_env, t0, t1); \
if (isfloat) { \
gen_helper_frsp(t2, cpu_env, t2); \
} \
set_fpr(rD(ctx->opcode), t2); \ set_fpr(rD(ctx->opcode), t2); \
if (set_fprf) { \ if (set_fprf) { \
gen_compute_fprf_float64(t2); \ gen_compute_fprf_float64(t2); \
@ -132,8 +129,8 @@ static void gen_f##name(DisasContext *ctx) \
tcg_temp_free_i64(t2); \ tcg_temp_free_i64(t2); \
} }
#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ _GEN_FLOAT_AC(name, 0x3F, op2, inval, set_fprf, type); \
_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); _GEN_FLOAT_AC(name##s, 0x3B, op2, inval, set_fprf, type);
#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
static void gen_f##name(DisasContext *ctx) \ static void gen_f##name(DisasContext *ctx) \