From 7f7a585d5bd3c7f1275d28c77d9d67513c1de36c Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Wed, 13 Nov 2019 15:54:35 +0100 Subject: [PATCH] target/i386: add PSCHANGE_NO bit for the ARCH_CAPABILITIES MSR This is required to disable ITLB multihit mitigations in nested hypervisors. Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index a624163ac2..2f60df37c4 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1204,7 +1204,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .type = MSR_FEATURE_WORD, .feat_names = { "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", - "ssb-no", "mds-no", NULL, NULL, + "ssb-no", "mds-no", "pschange-mc-no", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,