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Hexagon HVX (target/hexagon) helper overrides - vector logical ops 

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
This commit is contained in:
Taylor Simpson 2021-08-03 13:36:42 -05:00
parent 2c8ffa8f82
commit 7f4808ec99
1 changed files with 42 additions and 0 deletions
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42
target/hexagon/gen_tcg_hvx.h
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@ -361,4 +361,46 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
tcg_gen_gvec_umin(MO_8, VdV_off, VuV_off, VvV_off, \
sizeof(MMVector), sizeof(MMVector))
/* Vector logical ops */
#define fGEN_TCG_V6_vxor(SHORTCODE) \
tcg_gen_gvec_xor(MO_64, VdV_off, VuV_off, VvV_off, \
sizeof(MMVector), sizeof(MMVector))
#define fGEN_TCG_V6_vand(SHORTCODE) \
tcg_gen_gvec_and(MO_64, VdV_off, VuV_off, VvV_off, \
sizeof(MMVector), sizeof(MMVector))
#define fGEN_TCG_V6_vor(SHORTCODE) \
tcg_gen_gvec_or(MO_64, VdV_off, VuV_off, VvV_off, \
sizeof(MMVector), sizeof(MMVector))
#define fGEN_TCG_V6_vnot(SHORTCODE) \
tcg_gen_gvec_not(MO_64, VdV_off, VuV_off, \
sizeof(MMVector), sizeof(MMVector))
/* Q register logical ops */
#define fGEN_TCG_V6_pred_or(SHORTCODE) \
tcg_gen_gvec_or(MO_64, QdV_off, QsV_off, QtV_off, \
sizeof(MMQReg), sizeof(MMQReg))
#define fGEN_TCG_V6_pred_and(SHORTCODE) \
tcg_gen_gvec_and(MO_64, QdV_off, QsV_off, QtV_off, \
sizeof(MMQReg), sizeof(MMQReg))
#define fGEN_TCG_V6_pred_xor(SHORTCODE) \
tcg_gen_gvec_xor(MO_64, QdV_off, QsV_off, QtV_off, \
sizeof(MMQReg), sizeof(MMQReg))
#define fGEN_TCG_V6_pred_or_n(SHORTCODE) \
tcg_gen_gvec_orc(MO_64, QdV_off, QsV_off, QtV_off, \
sizeof(MMQReg), sizeof(MMQReg))
#define fGEN_TCG_V6_pred_and_n(SHORTCODE) \
tcg_gen_gvec_andc(MO_64, QdV_off, QsV_off, QtV_off, \
sizeof(MMQReg), sizeof(MMQReg))
#define fGEN_TCG_V6_pred_not(SHORTCODE) \
tcg_gen_gvec_not(MO_64, QdV_off, QsV_off, \
sizeof(MMQReg), sizeof(MMQReg))
#endif