mirror of https://github.com/xemu-project/xemu.git
target/sparc: Move gen_ne_fop_FFF insns to decodetree
Move FANDNOT1s, FANDNOT2s, FANDs, FNANDs, FNORs, FORNOT1s, FORNOT2s, FORs, FPADD16s, FPADD32s, FPSUB16s, FPSUB32s, FXNORs, FXORs. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
fafba1bb0b
commit
7f10b52f7b
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@ -37,6 +37,7 @@ CALL 01 i:s30
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&r_r_r rd rs1 rs2
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@r_r_r .. rd:5 ...... rs1:5 . ........ rs2:5 &r_r_r
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@r_r_r_swap .. rd:5 ...... rs2:5 . ........ rs1:5 &r_r_r
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&r_r rd rs
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@r_r1 .. rd:5 ...... rs:5 . ........ ..... &r_r
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@ -277,6 +278,21 @@ FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2
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FNOTs 10 ..... 110110 ..... 0 0110 1011 00000 @r_r1 # FNOT1s
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FNOTd 10 ..... 110110 00000 0 0110 0110 ..... @r_r2 # FNOT2d
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FNOTs 10 ..... 110110 00000 0 0110 0111 ..... @r_r2 # FNOT2s
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FPADD16s 10 ..... 110110 ..... 0 0101 0001 ..... @r_r_r
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FPADD32s 10 ..... 110110 ..... 0 0101 0011 ..... @r_r_r
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FPSUB16s 10 ..... 110110 ..... 0 0101 0101 ..... @r_r_r
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FPSUB32s 10 ..... 110110 ..... 0 0101 0111 ..... @r_r_r
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FNORs 10 ..... 110110 ..... 0 0110 0011 ..... @r_r_r
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FANDNOTs 10 ..... 110110 ..... 0 0110 0101 ..... @r_r_r # FANDNOT2s
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FANDNOTs 10 ..... 110110 ..... 0 0110 1001 ..... @r_r_r_swap # ... 1s
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FXORs 10 ..... 110110 ..... 0 0110 1101 ..... @r_r_r
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FNANDs 10 ..... 110110 ..... 0 0110 1111 ..... @r_r_r
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FANDs 10 ..... 110110 ..... 0 0111 0001 ..... @r_r_r
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FXNORs 10 ..... 110110 ..... 0 0111 0011 ..... @r_r_r
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FORNOTs 10 ..... 110110 ..... 0 0111 0111 ..... @r_r_r # FORNOT2s
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FORNOTs 10 ..... 110110 ..... 0 0111 1011 ..... @r_r_r_swap # ... 1s
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FORs 10 ..... 110110 ..... 0 0111 1101 ..... @r_r_r
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]
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NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1
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}
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@ -1628,22 +1628,6 @@ static void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
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gen_store_fpr_F(dc, rd, dst);
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}
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#ifdef TARGET_SPARC64
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static void gen_ne_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
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void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32))
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{
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TCGv_i32 dst, src1, src2;
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src1 = gen_load_fpr_F(dc, rs1);
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src2 = gen_load_fpr_F(dc, rs2);
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dst = gen_dest_fpr_F(dc);
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gen(dst, src1, src2);
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gen_store_fpr_F(dc, rd, dst);
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}
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#endif
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static void gen_fop_DD(DisasContext *dc, int rd, int rs,
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void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64))
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{
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@ -4855,6 +4839,35 @@ TRANS(FABSd, 64, do_dd, a, gen_op_fabsd)
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TRANS(FSRCd, VIS1, do_dd, a, tcg_gen_mov_i64)
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TRANS(FNOTd, VIS1, do_dd, a, tcg_gen_not_i64)
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static bool do_fff(DisasContext *dc, arg_r_r_r *a,
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void (*func)(TCGv_i32, TCGv_i32, TCGv_i32))
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{
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TCGv_i32 src1, src2;
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if (gen_trap_ifnofpu(dc)) {
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return true;
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}
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src1 = gen_load_fpr_F(dc, a->rs1);
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src2 = gen_load_fpr_F(dc, a->rs2);
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func(src1, src1, src2);
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gen_store_fpr_F(dc, a->rd, src1);
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return advance_pc(dc);
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}
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TRANS(FPADD16s, VIS1, do_fff, a, tcg_gen_vec_add16_i32)
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TRANS(FPADD32s, VIS1, do_fff, a, tcg_gen_add_i32)
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TRANS(FPSUB16s, VIS1, do_fff, a, tcg_gen_vec_sub16_i32)
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TRANS(FPSUB32s, VIS1, do_fff, a, tcg_gen_sub_i32)
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TRANS(FNORs, VIS1, do_fff, a, tcg_gen_nor_i32)
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TRANS(FANDNOTs, VIS1, do_fff, a, tcg_gen_andc_i32)
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TRANS(FXORs, VIS1, do_fff, a, tcg_gen_xor_i32)
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TRANS(FNANDs, VIS1, do_fff, a, tcg_gen_nand_i32)
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TRANS(FANDs, VIS1, do_fff, a, tcg_gen_and_i32)
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TRANS(FXNORs, VIS1, do_fff, a, tcg_gen_eqv_i32)
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TRANS(FORNOTs, VIS1, do_fff, a, tcg_gen_orc_i32)
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TRANS(FORs, VIS1, do_fff, a, tcg_gen_or_i32)
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#define CHECK_IU_FEATURE(dc, FEATURE) \
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if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
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goto illegal_insn;
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@ -5227,6 +5240,20 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
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case 0x06a: /* VIS I fnot1 */
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case 0x074: /* VIS I fsrc1 */
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case 0x078: /* VIS I fsrc2 */
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case 0x051: /* VIS I fpadd16s */
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case 0x053: /* VIS I fpadd32s */
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case 0x055: /* VIS I fpsub16s */
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case 0x057: /* VIS I fpsub32s */
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case 0x063: /* VIS I fnors */
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case 0x065: /* VIS I fandnot2s */
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case 0x069: /* VIS I fandnot1s */
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case 0x06d: /* VIS I fxors */
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case 0x06f: /* VIS I fnands */
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case 0x071: /* VIS I fands */
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case 0x073: /* VIS I fxnors */
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case 0x077: /* VIS I fornot2s */
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case 0x07b: /* VIS I fornot1s */
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case 0x07d: /* VIS I fors */
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g_assert_not_reached(); /* in decodetree */
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case 0x020: /* VIS I fcmple16 */
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CHECK_FPU_FEATURE(dc, VIS1);
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@ -5354,34 +5381,18 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
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CHECK_FPU_FEATURE(dc, VIS1);
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gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add16_i64);
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break;
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case 0x051: /* VIS I fpadd16s */
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CHECK_FPU_FEATURE(dc, VIS1);
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gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_vec_add16_i32);
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break;
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case 0x052: /* VIS I fpadd32 */
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CHECK_FPU_FEATURE(dc, VIS1);
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gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add32_i64);
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break;
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case 0x053: /* VIS I fpadd32s */
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CHECK_FPU_FEATURE(dc, VIS1);
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gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_add_i32);
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break;
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case 0x054: /* VIS I fpsub16 */
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CHECK_FPU_FEATURE(dc, VIS1);
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gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_sub16_i64);
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break;
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case 0x055: /* VIS I fpsub16s */
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CHECK_FPU_FEATURE(dc, VIS1);
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gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_vec_sub16_i32);
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break;
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case 0x056: /* VIS I fpsub32 */
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CHECK_FPU_FEATURE(dc, VIS1);
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gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add32_i64);
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break;
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case 0x057: /* VIS I fpsub32s */
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CHECK_FPU_FEATURE(dc, VIS1);
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gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_sub_i32);
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break;
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case 0x060: /* VIS I fzero */
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CHECK_FPU_FEATURE(dc, VIS1);
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cpu_dst_64 = gen_dest_fpr_D(dc, rd);
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@ -5398,83 +5409,42 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
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CHECK_FPU_FEATURE(dc, VIS1);
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gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nor_i64);
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break;
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case 0x063: /* VIS I fnors */
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CHECK_FPU_FEATURE(dc, VIS1);
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gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nor_i32);
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break;
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case 0x064: /* VIS I fandnot2 */
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CHECK_FPU_FEATURE(dc, VIS1);
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gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_andc_i64);
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break;
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case 0x065: /* VIS I fandnot2s */
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CHECK_FPU_FEATURE(dc, VIS1);
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gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_andc_i32);
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break;
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case 0x068: /* VIS I fandnot1 */
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CHECK_FPU_FEATURE(dc, VIS1);
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gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64);
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break;
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case 0x069: /* VIS I fandnot1s */
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CHECK_FPU_FEATURE(dc, VIS1);
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gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_andc_i32);
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break;
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case 0x06c: /* VIS I fxor */
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CHECK_FPU_FEATURE(dc, VIS1);
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gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64);
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break;
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case 0x06d: /* VIS I fxors */
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CHECK_FPU_FEATURE(dc, VIS1);
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gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_xor_i32);
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break;
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case 0x06e: /* VIS I fnand */
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CHECK_FPU_FEATURE(dc, VIS1);
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gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nand_i64);
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break;
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case 0x06f: /* VIS I fnands */
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CHECK_FPU_FEATURE(dc, VIS1);
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gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nand_i32);
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break;
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case 0x070: /* VIS I fand */
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CHECK_FPU_FEATURE(dc, VIS1);
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gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_and_i64);
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break;
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case 0x071: /* VIS I fands */
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CHECK_FPU_FEATURE(dc, VIS1);
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gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_and_i32);
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break;
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case 0x072: /* VIS I fxnor */
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CHECK_FPU_FEATURE(dc, VIS1);
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gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_eqv_i64);
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break;
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case 0x073: /* VIS I fxnors */
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CHECK_FPU_FEATURE(dc, VIS1);
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gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_eqv_i32);
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break;
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break;
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case 0x076: /* VIS I fornot2 */
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CHECK_FPU_FEATURE(dc, VIS1);
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gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_orc_i64);
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break;
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case 0x077: /* VIS I fornot2s */
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CHECK_FPU_FEATURE(dc, VIS1);
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gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_orc_i32);
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break;
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case 0x07a: /* VIS I fornot1 */
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CHECK_FPU_FEATURE(dc, VIS1);
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gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64);
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break;
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case 0x07b: /* VIS I fornot1s */
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CHECK_FPU_FEATURE(dc, VIS1);
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gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_orc_i32);
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break;
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case 0x07c: /* VIS I for */
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CHECK_FPU_FEATURE(dc, VIS1);
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gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_or_i64);
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break;
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case 0x07d: /* VIS I fors */
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CHECK_FPU_FEATURE(dc, VIS1);
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gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_or_i32);
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break;
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case 0x07e: /* VIS I fone */
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CHECK_FPU_FEATURE(dc, VIS1);
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cpu_dst_64 = gen_dest_fpr_D(dc, rd);
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