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hw/isa/piix: Share PIIX3's base class with PIIX4 

Having a common base class will allow for futher code sharing between PIIX3 and
PIIX4. Moreover, it makes PIIX4 implement the acpi-dev-aml-interface.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-24-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Bernhard Beschow 2023-10-07 14:38:31 +02:00 committed by Michael S. Tsirkin
parent f97479cad8
commit 7d6f26594b
1 changed files with 30 additions and 55 deletions
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85
hw/isa/piix.c
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@ -38,10 +38,6 @@
#include "migration/vmstate.h" #include "migration/vmstate.h"
#include "hw/acpi/acpi_aml_interface.h" #include "hw/acpi/acpi_aml_interface.h"
typedef struct PIIXState PIIX4State;
DECLARE_INSTANCE_CHECKER(PIIX4State, PIIX4_PCI_DEVICE, TYPE_PIIX4_PCI_DEVICE)
static void piix3_set_irq_pic(PIIXState *piix3, int pic_irq) static void piix3_set_irq_pic(PIIXState *piix3, int pic_irq)
{ {
qemu_set_irq(piix3->isa_irqs_in[pic_irq], qemu_set_irq(piix3->isa_irqs_in[pic_irq],
@ -88,7 +84,7 @@ static void piix3_set_irq(void *opaque, int pirq, int level)
static void piix4_set_irq(void *opaque, int irq_num, int level) static void piix4_set_irq(void *opaque, int irq_num, int level)
{ {
int i, pic_irq, pic_level; int i, pic_irq, pic_level;
PIIX4State *s = opaque; PIIXState *s = opaque;
PCIBus *bus = pci_get_bus(&s->dev); PCIBus *bus = pci_get_bus(&s->dev);
/* now we change the pic irq level according to the piix irq mappings */ /* now we change the pic irq level according to the piix irq mappings */
@ -108,7 +104,7 @@ static void piix4_set_irq(void *opaque, int irq_num, int level)
static void piix_request_i8259_irq(void *opaque, int irq, int level) static void piix_request_i8259_irq(void *opaque, int irq, int level)
{ {
PIIX4State *s = opaque; PIIXState *s = opaque;
qemu_set_irq(s->cpu_intr, level); qemu_set_irq(s->cpu_intr, level);
} }
@ -156,8 +152,9 @@ static void piix3_write_config(PCIDevice *dev,
} }
} }
static void piix_reset(PIIXState *d) static void piix_reset(DeviceState *dev)
{ {
PIIXState *d = PIIX_PCI_DEVICE(dev);
uint8_t *pci_conf = d->dev.config; uint8_t *pci_conf = d->dev.config;
pci_conf[0x04] = 0x07; /* master, memory and I/O */ pci_conf[0x04] = 0x07; /* master, memory and I/O */
@ -196,13 +193,6 @@ static void piix_reset(PIIXState *d)
d->rcr = 0; d->rcr = 0;
} }
static void piix3_reset(DeviceState *dev)
{
PIIXState *d = PIIX_PCI_DEVICE(dev);
piix_reset(d);
}
static int piix3_post_load(void *opaque, int version_id) static int piix3_post_load(void *opaque, int version_id)
{ {
PIIXState *piix3 = opaque; PIIXState *piix3 = opaque;
@ -227,7 +217,7 @@ static int piix3_post_load(void *opaque, int version_id)
static int piix4_post_load(void *opaque, int version_id) static int piix4_post_load(void *opaque, int version_id)
{ {
PIIX4State *s = opaque; PIIXState *s = opaque;
if (version_id == 2) { if (version_id == 2) {
s->rcr = 0; s->rcr = 0;
@ -291,8 +281,8 @@ static const VMStateDescription vmstate_piix4 = {
.minimum_version_id = 2, .minimum_version_id = 2,
.post_load = piix4_post_load, .post_load = piix4_post_load,
.fields = (VMStateField[]) { .fields = (VMStateField[]) {
VMSTATE_PCI_DEVICE(dev, PIIX4State), VMSTATE_PCI_DEVICE(dev, PIIXState),
VMSTATE_UINT8_V(rcr, PIIX4State, 3), VMSTATE_UINT8_V(rcr, PIIXState, 3),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
} }
}; };
@ -426,7 +416,7 @@ static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
qbus_build_aml(bus, scope); qbus_build_aml(bus, scope);
} }
static void pci_piix3_init(Object *obj) static void pci_piix_init(Object *obj)
{ {
PIIXState *d = PIIX_PCI_DEVICE(obj); PIIXState *d = PIIX_PCI_DEVICE(obj);
@ -434,7 +424,6 @@ static void pci_piix3_init(Object *obj)
ISA_NUM_IRQS); ISA_NUM_IRQS);
object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC);
object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE);
} }
static Property pci_piix3_props[] = { static Property pci_piix3_props[] = {
@ -447,27 +436,22 @@ static Property pci_piix3_props[] = {
DEFINE_PROP_END_OF_LIST(), DEFINE_PROP_END_OF_LIST(),
}; };
static void pci_piix3_class_init(ObjectClass *klass, void *data) static void pci_piix_class_init(ObjectClass *klass, void *data)
{ {
DeviceClass *dc = DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass); AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
k->config_write = piix3_write_config; dc->reset = piix_reset;
dc->reset = piix3_reset;
dc->desc = "ISA bridge"; dc->desc = "ISA bridge";
dc->vmsd = &vmstate_piix3;
dc->hotpluggable = false; dc->hotpluggable = false;
k->vendor_id = PCI_VENDOR_ID_INTEL; k->vendor_id = PCI_VENDOR_ID_INTEL;
/* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
k->class_id = PCI_CLASS_BRIDGE_ISA; k->class_id = PCI_CLASS_BRIDGE_ISA;
/* /*
* Reason: part of PIIX3 southbridge, needs to be wired up by * Reason: part of PIIX southbridge, needs to be wired up by e.g.
* pc_piix.c's pc_init1() * pc_piix.c's pc_init1()
*/ */
dc->user_creatable = false; dc->user_creatable = false;
device_class_set_props(dc, pci_piix3_props);
adevc->build_dev_aml = build_pci_isa_aml; adevc->build_dev_aml = build_pci_isa_aml;
} }
@ -475,9 +459,9 @@ static const TypeInfo piix_pci_type_info = {
.name = TYPE_PIIX_PCI_DEVICE, .name = TYPE_PIIX_PCI_DEVICE,
.parent = TYPE_PCI_DEVICE, .parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PIIXState), .instance_size = sizeof(PIIXState),
.instance_init = pci_piix3_init, .instance_init = pci_piix_init,
.abstract = true, .abstract = true,
.class_init = pci_piix3_class_init, .class_init = pci_piix_class_init,
.interfaces = (InterfaceInfo[]) { .interfaces = (InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE }, { INTERFACE_CONVENTIONAL_PCI_DEVICE },
{ TYPE_ACPI_DEV_AML_IF }, { TYPE_ACPI_DEV_AML_IF },
@ -500,22 +484,36 @@ static void piix3_realize(PCIDevice *dev, Error **errp)
pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
} }
static void piix3_init(Object *obj)
{
PIIXState *d = PIIX_PCI_DEVICE(obj);
object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE);
}
static void piix3_class_init(ObjectClass *klass, void *data) static void piix3_class_init(ObjectClass *klass, void *data)
{ {
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->config_write = piix3_write_config;
k->realize = piix3_realize; k->realize = piix3_realize;
/* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
dc->vmsd = &vmstate_piix3;
device_class_set_props(dc, pci_piix3_props);
} }
static const TypeInfo piix3_info = { static const TypeInfo piix3_info = {
.name = TYPE_PIIX3_DEVICE, .name = TYPE_PIIX3_DEVICE,
.parent = TYPE_PIIX_PCI_DEVICE, .parent = TYPE_PIIX_PCI_DEVICE,
.instance_init = piix3_init,
.class_init = piix3_class_init, .class_init = piix3_class_init,
}; };
static void piix4_realize(PCIDevice *dev, Error **errp) static void piix4_realize(PCIDevice *dev, Error **errp)
{ {
PIIX4State *s = PIIX4_PCI_DEVICE(dev); PIIXState *s = PIIX_PCI_DEVICE(dev);
PCIBus *pci_bus = pci_get_bus(dev); PCIBus *pci_bus = pci_get_bus(dev);
ISABus *isa_bus; ISABus *isa_bus;
qemu_irq *i8259_out_irq; qemu_irq *i8259_out_irq;
@ -584,18 +582,10 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS); pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS);
} }
static void piix4_isa_reset(DeviceState *dev)
{
PIIX4State *s = PIIX4_PCI_DEVICE(dev);
piix_reset(s);
}
static void piix4_init(Object *obj) static void piix4_init(Object *obj)
{ {
PIIX4State *s = PIIX4_PCI_DEVICE(obj); PIIXState *s = PIIX_PCI_DEVICE(obj);
object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC);
object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE); object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE);
object_initialize_child(obj, "uhci", &s->uhci, TYPE_PIIX4_USB_UHCI); object_initialize_child(obj, "uhci", &s->uhci, TYPE_PIIX4_USB_UHCI);
@ -610,30 +600,15 @@ static void piix4_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->realize = piix4_realize; k->realize = piix4_realize;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0; k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
k->class_id = PCI_CLASS_BRIDGE_ISA;
dc->reset = piix4_isa_reset;
dc->desc = "ISA bridge";
dc->vmsd = &vmstate_piix4; dc->vmsd = &vmstate_piix4;
/*
* Reason: part of PIIX4 southbridge, needs to be wired up,
* e.g. by mips_malta_init()
*/
dc->user_creatable = false;
dc->hotpluggable = false;
} }
static const TypeInfo piix4_info = { static const TypeInfo piix4_info = {
.name = TYPE_PIIX4_PCI_DEVICE, .name = TYPE_PIIX4_PCI_DEVICE,
.parent = TYPE_PCI_DEVICE, .parent = TYPE_PIIX_PCI_DEVICE,
.instance_size = sizeof(PIIX4State),
.instance_init = piix4_init, .instance_init = piix4_init,
.class_init = piix4_class_init, .class_init = piix4_class_init,
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
{ },
},
}; };
static void piix3_register_types(void) static void piix3_register_types(void)