mirror of https://github.com/xemu-project/xemu.git
Revert "linux-user/arm: Take more care allocating commpage"
accel/tcg: Fix jump cache set in cpu_exec_loop accel/tcg: Fix initialization of CF_PCREL in tcg_cflags tcg/sparc64: Disable direct jumps from goto_tb -----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmQsRwAdHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV8QqQf6AnUwdkp0zEUevshL gPlns3u5RZIv/i5L1VIkYrLbaFQtwD17CfBACB2MxZI6lbPK4jT++FlDiWJ1ak7i 4p9Q5KOAbjAxQgQXy51NbEzg5AoIYP5HEg2cnjfEg0PltRVTn0bdbBVbCG/erDXa NfEOPtHSU+6B8jRjp0MRvFv4Y4CJ3nQ7eZ6TMI3oGOk44DOs22Fn330E8wT2vpt4 ayJNDN8F0FZ5wGZdJIAsMSgauaGJwY/ZG1KX8TGQb7nsRn5lbpEgoOUCd0WUGdx6 3YsoELaZoHZhAlvVNjbOMBp3fZSH2owb08By9vU7ZMjPOnsjZQz6TuxR6NNl+04G tPi44Q== =+m7M -----END PGP SIGNATURE----- Merge tag 'pull-tcg-20230404' of https://gitlab.com/rth7680/qemu into staging Revert "linux-user/arm: Take more care allocating commpage" accel/tcg: Fix jump cache set in cpu_exec_loop accel/tcg: Fix initialization of CF_PCREL in tcg_cflags tcg/sparc64: Disable direct jumps from goto_tb # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmQsRwAdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV8QqQf6AnUwdkp0zEUevshL # gPlns3u5RZIv/i5L1VIkYrLbaFQtwD17CfBACB2MxZI6lbPK4jT++FlDiWJ1ak7i # 4p9Q5KOAbjAxQgQXy51NbEzg5AoIYP5HEg2cnjfEg0PltRVTn0bdbBVbCG/erDXa # NfEOPtHSU+6B8jRjp0MRvFv4Y4CJ3nQ7eZ6TMI3oGOk44DOs22Fn330E8wT2vpt4 # ayJNDN8F0FZ5wGZdJIAsMSgauaGJwY/ZG1KX8TGQb7nsRn5lbpEgoOUCd0WUGdx6 # 3YsoELaZoHZhAlvVNjbOMBp3fZSH2owb08By9vU7ZMjPOnsjZQz6TuxR6NNl+04G # tPi44Q== # =+m7M # -----END PGP SIGNATURE----- # gpg: Signature made Tue 04 Apr 2023 16:49:20 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20230404' of https://gitlab.com/rth7680/qemu: tcg/sparc64: Disable direct linking for goto_tb accel/tcg: Fix jump cache set in cpu_exec_loop accel/tcg: Fix overwrite problems of tcg_cflags Revert "linux-user/arm: Take more care allocating commpage" Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
7d0334e491
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@ -257,7 +257,7 @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc,
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if (cflags & CF_PCREL) {
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/* Use acquire to ensure current load of pc from jc. */
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tb = qatomic_load_acquire(&jc->array[hash].tb);
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tb = qatomic_load_acquire(&jc->array[hash].tb);
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if (likely(tb &&
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jc->array[hash].pc == pc &&
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@ -272,7 +272,7 @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc,
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return NULL;
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}
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jc->array[hash].pc = pc;
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/* Use store_release on tb to ensure pc is written first. */
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/* Ensure pc is written first. */
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qatomic_store_release(&jc->array[hash].tb, tb);
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} else {
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/* Use rcu_read to ensure current load of pc from *tb. */
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@ -971,18 +971,27 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc)
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tb = tb_lookup(cpu, pc, cs_base, flags, cflags);
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if (tb == NULL) {
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CPUJumpCache *jc;
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uint32_t h;
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mmap_lock();
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tb = tb_gen_code(cpu, pc, cs_base, flags, cflags);
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mmap_unlock();
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/*
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* We add the TB in the virtual pc hash table
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* for the fast lookup
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*/
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h = tb_jmp_cache_hash_func(pc);
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/* Use the pc value already stored in tb->pc. */
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qatomic_set(&cpu->tb_jmp_cache->array[h].tb, tb);
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jc = cpu->tb_jmp_cache;
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if (cflags & CF_PCREL) {
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jc->array[h].pc = pc;
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/* Ensure pc is written first. */
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qatomic_store_release(&jc->array[h].tb, tb);
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} else {
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/* Use the pc value already stored in tb->pc. */
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qatomic_set(&jc->array[h].tb, tb);
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}
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}
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#ifndef CONFIG_USER_ONLY
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@ -59,7 +59,7 @@ void tcg_cpu_init_cflags(CPUState *cpu, bool parallel)
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cflags |= parallel ? CF_PARALLEL : 0;
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cflags |= icount_enabled() ? CF_USE_ICOUNT : 0;
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cpu->tcg_cflags = cflags;
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cpu->tcg_cflags |= cflags;
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}
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void tcg_cpus_destroy(CPUState *cpu)
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@ -423,32 +423,12 @@ enum {
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static bool init_guest_commpage(void)
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{
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ARMCPU *cpu = ARM_CPU(thread_cpu);
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abi_ptr want = HI_COMMPAGE & TARGET_PAGE_MASK;
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abi_ptr addr;
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abi_ptr commpage = HI_COMMPAGE & -qemu_host_page_size;
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void *want = g2h_untagged(commpage);
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void *addr = mmap(want, qemu_host_page_size, PROT_READ | PROT_WRITE,
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MAP_ANONYMOUS | MAP_PRIVATE | MAP_FIXED, -1, 0);
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/*
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* M-profile allocates maximum of 2GB address space, so can never
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* allocate the commpage. Skip it.
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*/
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if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
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return true;
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}
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/*
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* If reserved_va does not cover the commpage, we get an assert
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* in page_set_flags. Produce an intelligent error instead.
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*/
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if (reserved_va != 0 && want + TARGET_PAGE_SIZE - 1 > reserved_va) {
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error_report("Allocating guest commpage: -R 0x%" PRIx64 " too small",
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(uint64_t)reserved_va + 1);
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exit(EXIT_FAILURE);
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}
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addr = target_mmap(want, TARGET_PAGE_SIZE, PROT_READ | PROT_WRITE,
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MAP_ANONYMOUS | MAP_PRIVATE | MAP_FIXED, -1, 0);
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if (addr == -1) {
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if (addr == MAP_FAILED) {
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perror("Allocating guest commpage");
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exit(EXIT_FAILURE);
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}
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@ -457,12 +437,15 @@ static bool init_guest_commpage(void)
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}
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/* Set kernel helper versions; rest of page is 0. */
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put_user_u32(5, 0xffff0ffcu);
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__put_user(5, (uint32_t *)g2h_untagged(0xffff0ffcu));
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if (target_mprotect(addr, qemu_host_page_size, PROT_READ | PROT_EXEC)) {
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if (mprotect(addr, qemu_host_page_size, PROT_READ)) {
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perror("Protecting guest commpage");
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exit(EXIT_FAILURE);
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}
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page_set_flags(commpage, commpage | ~qemu_host_page_mask,
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PAGE_READ | PAGE_EXEC | PAGE_VALID);
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return true;
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}
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@ -1445,12 +1445,12 @@ static void tcg_out_goto_tb(TCGContext *s, int which)
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{
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ptrdiff_t off = tcg_tbrel_diff(s, (void *)get_jmp_target_addr(s, which));
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/* Direct branch will be patched by tb_target_set_jmp_target. */
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/* Load link and indirect branch. */
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set_jmp_insn_offset(s, which);
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tcg_out32(s, CALL);
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/* delay slot */
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tcg_debug_assert(check_fit_ptr(off, 13));
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, TCG_REG_TB, off);
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tcg_out_arithi(s, TCG_REG_G0, TCG_REG_TB, 0, JMPL);
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/* delay slot */
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tcg_out_nop(s);
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set_jmp_reset_offset(s, which);
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/*
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@ -1469,28 +1469,6 @@ static void tcg_out_goto_tb(TCGContext *s, int which)
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void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
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uintptr_t jmp_rx, uintptr_t jmp_rw)
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{
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uintptr_t addr = tb->jmp_target_addr[n];
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intptr_t br_disp = (intptr_t)(addr - jmp_rx) >> 2;
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tcg_insn_unit insn;
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br_disp >>= 2;
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if (check_fit_ptr(br_disp, 19)) {
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/* ba,pt %icc, addr */
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insn = deposit32(INSN_OP(0) | INSN_OP2(1) | INSN_COND(COND_A)
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| BPCC_ICC | BPCC_PT, 0, 19, br_disp);
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} else if (check_fit_ptr(br_disp, 22)) {
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/* ba addr */
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insn = deposit32(INSN_OP(0) | INSN_OP2(2) | INSN_COND(COND_A),
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0, 22, br_disp);
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} else {
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/* The code_gen_buffer can't be larger than 2GB. */
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tcg_debug_assert(check_fit_ptr(br_disp, 30));
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/* call addr */
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insn = deposit32(CALL, 0, 30, br_disp);
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}
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qatomic_set((uint32_t *)jmp_rw, insn);
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flush_idcache_range(jmp_rx, jmp_rw, 4);
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}
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static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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