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target/avr: Support probe argument to tlb_fill 

While there are no target-specific nonfaulting probes,
generic code may grow some uses at some point.

Note that the attrs argument was incorrect -- it should have
been MEMTXATTRS_UNSPECIFIED. Just use the simpler interface.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-08-22 21:57:20 -07:00
parent e93ded1bf6
commit 7bccb9e322
1 changed files with 29 additions and 17 deletions
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46
target/avr/helper.c
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@ -102,38 +102,50 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx, MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr) bool probe, uintptr_t retaddr)
{ {
int prot = 0; int prot, page_size = TARGET_PAGE_SIZE;
MemTxAttrs attrs = {};
uint32_t paddr; uint32_t paddr;
address &= TARGET_PAGE_MASK; address &= TARGET_PAGE_MASK;
if (mmu_idx == MMU_CODE_IDX) { if (mmu_idx == MMU_CODE_IDX) {
/* access to code in flash */ /* Access to code in flash. */
paddr = OFFSET_CODE + address; paddr = OFFSET_CODE + address;
prot = PAGE_READ | PAGE_EXEC; prot = PAGE_READ | PAGE_EXEC;
if (paddr + TARGET_PAGE_SIZE > OFFSET_DATA) { if (paddr >= OFFSET_DATA) {
/*
* This should not be possible via any architectural operations.
* There is certainly not an exception that we can deliver.
* Accept probing that might come from generic code.
*/
if (probe) {
return false;
}
error_report("execution left flash memory"); error_report("execution left flash memory");
abort(); abort();
} }
} else if (address < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
/*
* access to CPU registers, exit and rebuilt this TB to use full access
* incase it touches specially handled registers like SREG or SP
*/
AVRCPU *cpu = AVR_CPU(cs);
CPUAVRState *env = &cpu->env;
env->fullacc = 1;
cpu_loop_exit_restore(cs, retaddr);
} else { } else {
/* access to memory. nothing special */ /* Access to memory. */
paddr = OFFSET_DATA + address; paddr = OFFSET_DATA + address;
prot = PAGE_READ | PAGE_WRITE; prot = PAGE_READ | PAGE_WRITE;
if (address < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
/*
* Access to CPU registers, exit and rebuilt this TB to use
* full access in case it touches specially handled registers
* like SREG or SP. For probing, set page_size = 1, in order
* to force tlb_fill to be called for the next access.
*/
if (probe) {
page_size = 1;
} else {
AVRCPU *cpu = AVR_CPU(cs);
CPUAVRState *env = &cpu->env;
env->fullacc = 1;
cpu_loop_exit_restore(cs, retaddr);
}
}
} }
tlb_set_page_with_attrs(cs, address, paddr, attrs, prot, tlb_set_page(cs, address, paddr, prot, mmu_idx, page_size);
mmu_idx, TARGET_PAGE_SIZE);
return true; return true;
} }