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m48t59: Rename "type" property to "model" 

This resolves a name conflict with the qdev "type" property that is
about to move into Object.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
[AF: Add braces missing in original code.]
Signed-off-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Paolo Bonzini 2012-05-23 19:25:34 +02:00 committed by Andreas Färber
parent 049cb3cfda
commit 7bc3018b32
1 changed files with 22 additions and 18 deletions
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40
hw/m48t59.c
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@ -65,7 +65,7 @@ struct M48t59State {
/* NVRAM storage */ /* NVRAM storage */
uint8_t *buffer; uint8_t *buffer;
/* Model parameters */ /* Model parameters */
uint32_t type; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */ uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
/* NVRAM storage */ /* NVRAM storage */
uint16_t addr; uint16_t addr;
uint8_t lock; uint8_t lock;
@ -197,10 +197,11 @@ void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val); NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
/* check for NVRAM access */ /* check for NVRAM access */
if ((NVRAM->type == 2 && addr < 0x7f8) || if ((NVRAM->model == 2 && addr < 0x7f8) ||
(NVRAM->type == 8 && addr < 0x1ff8) || (NVRAM->model == 8 && addr < 0x1ff8) ||
(NVRAM->type == 59 && addr < 0x1ff0)) (NVRAM->model == 59 && addr < 0x1ff0)) {
goto do_write; goto do_write;
}
/* TOD access */ /* TOD access */
switch (addr) { switch (addr) {
@ -334,10 +335,11 @@ void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
tmp = from_bcd(val); tmp = from_bcd(val);
if (tmp >= 0 && tmp <= 99) { if (tmp >= 0 && tmp <= 99) {
get_time(NVRAM, &tm); get_time(NVRAM, &tm);
if (NVRAM->type == 8) if (NVRAM->model == 8) {
tm.tm_year = from_bcd(val) + 68; // Base year is 1968 tm.tm_year = from_bcd(val) + 68; // Base year is 1968
else } else {
tm.tm_year = from_bcd(val); tm.tm_year = from_bcd(val);
}
set_time(NVRAM, &tm); set_time(NVRAM, &tm);
} }
break; break;
@ -362,10 +364,11 @@ uint32_t m48t59_read (void *opaque, uint32_t addr)
uint32_t retval = 0xFF; uint32_t retval = 0xFF;
/* check for NVRAM access */ /* check for NVRAM access */
if ((NVRAM->type == 2 && addr < 0x078f) || if ((NVRAM->model == 2 && addr < 0x078f) ||
(NVRAM->type == 8 && addr < 0x1ff8) || (NVRAM->model == 8 && addr < 0x1ff8) ||
(NVRAM->type == 59 && addr < 0x1ff0)) (NVRAM->model == 59 && addr < 0x1ff0)) {
goto do_read; goto do_read;
}
/* TOD access */ /* TOD access */
switch (addr) { switch (addr) {
@ -439,10 +442,11 @@ uint32_t m48t59_read (void *opaque, uint32_t addr)
case 0x07FF: case 0x07FF:
/* year */ /* year */
get_time(NVRAM, &tm); get_time(NVRAM, &tm);
if (NVRAM->type == 8) if (NVRAM->model == 8) {
retval = to_bcd(tm.tm_year - 68); // Base year is 1968 retval = to_bcd(tm.tm_year - 68); // Base year is 1968
else } else {
retval = to_bcd(tm.tm_year); retval = to_bcd(tm.tm_year);
}
break; break;
default: default:
/* Check lock registers state */ /* Check lock registers state */
@ -633,7 +637,7 @@ static const MemoryRegionOps m48t59_io_ops = {
/* Initialisation routine */ /* Initialisation routine */
M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base, M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base,
uint32_t io_base, uint16_t size, int type) uint32_t io_base, uint16_t size, int model)
{ {
DeviceState *dev; DeviceState *dev;
SysBusDevice *s; SysBusDevice *s;
@ -641,7 +645,7 @@ M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base,
M48t59State *state; M48t59State *state;
dev = qdev_create(NULL, "m48t59"); dev = qdev_create(NULL, "m48t59");
qdev_prop_set_uint32(dev, "type", type); qdev_prop_set_uint32(dev, "model", model);
qdev_prop_set_uint32(dev, "size", size); qdev_prop_set_uint32(dev, "size", size);
qdev_prop_set_uint32(dev, "io_base", io_base); qdev_prop_set_uint32(dev, "io_base", io_base);
qdev_init_nofail(dev); qdev_init_nofail(dev);
@ -661,14 +665,14 @@ M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base,
} }
M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size, M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
int type) int model)
{ {
M48t59ISAState *d; M48t59ISAState *d;
ISADevice *dev; ISADevice *dev;
M48t59State *s; M48t59State *s;
dev = isa_create(bus, "m48t59_isa"); dev = isa_create(bus, "m48t59_isa");
qdev_prop_set_uint32(&dev->qdev, "type", type); qdev_prop_set_uint32(&dev->qdev, "model", model);
qdev_prop_set_uint32(&dev->qdev, "size", size); qdev_prop_set_uint32(&dev->qdev, "size", size);
qdev_prop_set_uint32(&dev->qdev, "io_base", io_base); qdev_prop_set_uint32(&dev->qdev, "io_base", io_base);
qdev_init_nofail(&dev->qdev); qdev_init_nofail(&dev->qdev);
@ -686,7 +690,7 @@ M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
static void m48t59_init_common(M48t59State *s) static void m48t59_init_common(M48t59State *s)
{ {
s->buffer = g_malloc0(s->size); s->buffer = g_malloc0(s->size);
if (s->type == 59) { if (s->model == 59) {
s->alrm_timer = qemu_new_timer_ns(rtc_clock, &alarm_cb, s); s->alrm_timer = qemu_new_timer_ns(rtc_clock, &alarm_cb, s);
s->wd_timer = qemu_new_timer_ns(vm_clock, &watchdog_cb, s); s->wd_timer = qemu_new_timer_ns(vm_clock, &watchdog_cb, s);
} }
@ -722,7 +726,7 @@ static int m48t59_init1(SysBusDevice *dev)
static Property m48t59_isa_properties[] = { static Property m48t59_isa_properties[] = {
DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1), DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1),
DEFINE_PROP_UINT32("type", M48t59ISAState, state.type, -1), DEFINE_PROP_UINT32("model", M48t59ISAState, state.model, -1),
DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base, 0), DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base, 0),
DEFINE_PROP_END_OF_LIST(), DEFINE_PROP_END_OF_LIST(),
}; };
@ -746,7 +750,7 @@ static TypeInfo m48t59_isa_info = {
static Property m48t59_properties[] = { static Property m48t59_properties[] = {
DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1), DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1),
DEFINE_PROP_UINT32("type", M48t59SysBusState, state.type, -1), DEFINE_PROP_UINT32("model", M48t59SysBusState, state.model, -1),
DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base, 0), DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base, 0),
DEFINE_PROP_END_OF_LIST(), DEFINE_PROP_END_OF_LIST(),
}; };