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target/mips: Clean up internal.h 

Mostly fix errors and warnings reported by 'checkpatch.pl -f'.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <1569331602-2586-3-git-send-email-aleksandar.markovic@rt-rk.com>
This commit is contained in:
Aleksandar Markovic 2019-09-24 15:26:33 +02:00
parent 95e9d74fe4
commit 7ba0e95bca
1 changed files with 37 additions and 23 deletions
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60
target/mips/internal.h
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@ -1,4 +1,5 @@
/* mips internal definitions and helpers /*
* MIPS internal definitions and helpers
* *
* This work is licensed under the terms of the GNU GPL, version 2 or later. * This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory. * See the COPYING file in the top-level directory.
@ -9,8 +10,10 @@
#include "fpu/softfloat-helpers.h" #include "fpu/softfloat-helpers.h"
/* MMU types, the first four entries have the same layout as the /*
CP0C0_MT field. */ * MMU types, the first four entries have the same layout as the
* CP0C0_MT field.
*/
enum mips_mmu_types { enum mips_mmu_types {
MMU_TYPE_NONE, MMU_TYPE_NONE,
MMU_TYPE_R4000, MMU_TYPE_R4000,
@ -160,9 +163,11 @@ static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
!(env->CP0_Status & (1 << CP0St_EXL)) && !(env->CP0_Status & (1 << CP0St_EXL)) &&
!(env->CP0_Status & (1 << CP0St_ERL)) && !(env->CP0_Status & (1 << CP0St_ERL)) &&
!(env->hflags & MIPS_HFLAG_DM) && !(env->hflags & MIPS_HFLAG_DM) &&
/* Note that the TCStatus IXMT field is initialized to zero, /*
and only MT capable cores can set it to one. So we don't * Note that the TCStatus IXMT field is initialized to zero,
need to check for MT capabilities here. */ * and only MT capable cores can set it to one. So we don't
* need to check for MT capabilities here.
*/
!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)); !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
} }
@ -177,14 +182,18 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
status = env->CP0_Status & CP0Ca_IP_mask; status = env->CP0_Status & CP0Ca_IP_mask;
if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
/* A MIPS configured with a vectorizing external interrupt controller /*
will feed a vector into the Cause pending lines. The core treats * A MIPS configured with a vectorizing external interrupt controller
the status lines as a vector level, not as indiviual masks. */ * will feed a vector into the Cause pending lines. The core treats
* the status lines as a vector level, not as indiviual masks.
*/
r = pending > status; r = pending > status;
} else { } else {
/* A MIPS configured with compatibility or VInt (Vectored Interrupts) /*
treats the pending lines as individual interrupt lines, the status * A MIPS configured with compatibility or VInt (Vectored Interrupts)
lines are individual masks. */ * treats the pending lines as individual interrupt lines, the status
* lines are individual masks.
*/
r = (pending & status) != 0; r = (pending & status) != 0;
} }
return r; return r;
@ -275,12 +284,14 @@ static inline int mips_vpe_active(CPUMIPSState *env)
active = 0; active = 0;
} }
/* Now verify that there are active thread contexts in the VPE. /*
* Now verify that there are active thread contexts in the VPE.
This assumes the CPU model will internally reschedule threads *
if the active one goes to sleep. If there are no threads available * This assumes the CPU model will internally reschedule threads
the active one will be in a sleeping state, and we can turn off * if the active one goes to sleep. If there are no threads available
the entire VPE. */ * the active one will be in a sleeping state, and we can turn off
* the entire VPE.
*/
if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) { if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
/* TC is not activated. */ /* TC is not activated. */
active = 0; active = 0;
@ -326,7 +337,8 @@ static inline void compute_hflags(CPUMIPSState *env)
if (!(env->CP0_Status & (1 << CP0St_EXL)) && if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
!(env->CP0_Status & (1 << CP0St_ERL)) && !(env->CP0_Status & (1 << CP0St_ERL)) &&
!(env->hflags & MIPS_HFLAG_DM)) { !(env->hflags & MIPS_HFLAG_DM)) {
env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU; env->hflags |= (env->CP0_Status >> CP0St_KSU) &
MIPS_HFLAG_KSU;
} }
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
if ((env->insn_flags & ISA_MIPS3) && if ((env->insn_flags & ISA_MIPS3) &&
@ -403,10 +415,12 @@ static inline void compute_hflags(CPUMIPSState *env)
env->hflags |= MIPS_HFLAG_COP1X; env->hflags |= MIPS_HFLAG_COP1X;
} }
} else if (env->insn_flags & ISA_MIPS4) { } else if (env->insn_flags & ISA_MIPS4) {
/* All supported MIPS IV CPUs use the XX (CU3) to enable /*
and disable the MIPS IV extensions to the MIPS III ISA. * All supported MIPS IV CPUs use the XX (CU3) to enable
Some other MIPS IV CPUs ignore the bit, so the check here * and disable the MIPS IV extensions to the MIPS III ISA.
would be too restrictive for them. */ * Some other MIPS IV CPUs ignore the bit, so the check here
* would be too restrictive for them.
*/
if (env->CP0_Status & (1U << CP0St_CU3)) { if (env->CP0_Status & (1U << CP0St_CU3)) {
env->hflags |= MIPS_HFLAG_COP1X; env->hflags |= MIPS_HFLAG_COP1X;
} }