mirror of https://github.com/xemu-project/xemu.git
target/mips: Clean up internal.h
Mostly fix errors and warnings reported by 'checkpatch.pl -f'. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <1569331602-2586-3-git-send-email-aleksandar.markovic@rt-rk.com>
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@ -1,4 +1,5 @@
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/* mips internal definitions and helpers
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/*
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* MIPS internal definitions and helpers
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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@ -9,8 +10,10 @@
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#include "fpu/softfloat-helpers.h"
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/* MMU types, the first four entries have the same layout as the
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CP0C0_MT field. */
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/*
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* MMU types, the first four entries have the same layout as the
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* CP0C0_MT field.
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*/
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enum mips_mmu_types {
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MMU_TYPE_NONE,
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MMU_TYPE_R4000,
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@ -160,9 +163,11 @@ static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
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!(env->CP0_Status & (1 << CP0St_EXL)) &&
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!(env->CP0_Status & (1 << CP0St_ERL)) &&
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!(env->hflags & MIPS_HFLAG_DM) &&
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/* Note that the TCStatus IXMT field is initialized to zero,
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and only MT capable cores can set it to one. So we don't
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need to check for MT capabilities here. */
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/*
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* Note that the TCStatus IXMT field is initialized to zero,
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* and only MT capable cores can set it to one. So we don't
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* need to check for MT capabilities here.
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*/
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!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
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}
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@ -177,14 +182,18 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
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status = env->CP0_Status & CP0Ca_IP_mask;
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if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
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/* A MIPS configured with a vectorizing external interrupt controller
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will feed a vector into the Cause pending lines. The core treats
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the status lines as a vector level, not as indiviual masks. */
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/*
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* A MIPS configured with a vectorizing external interrupt controller
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* will feed a vector into the Cause pending lines. The core treats
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* the status lines as a vector level, not as indiviual masks.
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*/
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r = pending > status;
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} else {
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/* A MIPS configured with compatibility or VInt (Vectored Interrupts)
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treats the pending lines as individual interrupt lines, the status
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lines are individual masks. */
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/*
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* A MIPS configured with compatibility or VInt (Vectored Interrupts)
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* treats the pending lines as individual interrupt lines, the status
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* lines are individual masks.
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*/
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r = (pending & status) != 0;
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}
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return r;
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@ -275,12 +284,14 @@ static inline int mips_vpe_active(CPUMIPSState *env)
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active = 0;
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}
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/* Now verify that there are active thread contexts in the VPE.
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This assumes the CPU model will internally reschedule threads
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if the active one goes to sleep. If there are no threads available
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the active one will be in a sleeping state, and we can turn off
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the entire VPE. */
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/*
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* Now verify that there are active thread contexts in the VPE.
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*
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* This assumes the CPU model will internally reschedule threads
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* if the active one goes to sleep. If there are no threads available
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* the active one will be in a sleeping state, and we can turn off
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* the entire VPE.
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*/
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if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
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/* TC is not activated. */
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active = 0;
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@ -326,7 +337,8 @@ static inline void compute_hflags(CPUMIPSState *env)
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if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
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!(env->CP0_Status & (1 << CP0St_ERL)) &&
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!(env->hflags & MIPS_HFLAG_DM)) {
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env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
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env->hflags |= (env->CP0_Status >> CP0St_KSU) &
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MIPS_HFLAG_KSU;
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}
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#if defined(TARGET_MIPS64)
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if ((env->insn_flags & ISA_MIPS3) &&
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@ -403,10 +415,12 @@ static inline void compute_hflags(CPUMIPSState *env)
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env->hflags |= MIPS_HFLAG_COP1X;
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}
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} else if (env->insn_flags & ISA_MIPS4) {
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/* All supported MIPS IV CPUs use the XX (CU3) to enable
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and disable the MIPS IV extensions to the MIPS III ISA.
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Some other MIPS IV CPUs ignore the bit, so the check here
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would be too restrictive for them. */
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/*
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* All supported MIPS IV CPUs use the XX (CU3) to enable
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* and disable the MIPS IV extensions to the MIPS III ISA.
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* Some other MIPS IV CPUs ignore the bit, so the check here
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* would be too restrictive for them.
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*/
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if (env->CP0_Status & (1U << CP0St_CU3)) {
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env->hflags |= MIPS_HFLAG_COP1X;
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}
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