mirror of https://github.com/xemu-project/xemu.git
tcg-sparc: Implement add2, sub2, mulu2.
Add missing 32-bit double-word support opcodes. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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@ -215,6 +215,7 @@ static inline int tcg_target_const_match(tcg_target_long val,
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#define BA (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2))
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#define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00))
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#define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10))
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#define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01))
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#define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02))
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#define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12))
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@ -238,6 +239,7 @@ static inline int tcg_target_const_match(tcg_target_long val,
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#define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12))
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#define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12))
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#define RDY (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(0))
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#define WRY (INSN_OP(2) | INSN_OP3(0x30))
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#define JMPL (INSN_OP(2) | INSN_OP3(0x38))
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#define SAVE (INSN_OP(2) | INSN_OP3(0x3c))
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@ -410,6 +412,11 @@ static inline void tcg_out_sety(TCGContext *s, tcg_target_long val)
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fprintf(stderr, "unimplemented sety %ld\n", (long)val);
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}
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static inline void tcg_out_rdy(TCGContext *s, int rd)
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{
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tcg_out32(s, RDY | INSN_RD(rd));
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}
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static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
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{
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if (val != 0) {
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@ -1132,6 +1139,23 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
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args[2], const_args[2],
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args[3], const_args[3], args[5]);
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break;
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case INDEX_op_add2_i32:
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tcg_out_arithc(s, args[0], args[2], args[4], const_args[4],
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ARITH_ADDCC);
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tcg_out_arithc(s, args[1], args[3], args[5], const_args[5],
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ARITH_ADDX);
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break;
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case INDEX_op_sub2_i32:
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tcg_out_arithc(s, args[0], args[2], args[4], const_args[4],
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ARITH_SUBCC);
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tcg_out_arithc(s, args[1], args[3], args[5], const_args[5],
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ARITH_SUBX);
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break;
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case INDEX_op_mulu2_i32:
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tcg_out_arithc(s, args[0], args[2], args[3], const_args[3],
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ARITH_UMUL);
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tcg_out_rdy(s, args[1]);
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break;
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#endif
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case INDEX_op_qemu_ld8u:
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@ -1250,6 +1274,9 @@ static const TCGTargetOpDef sparc_op_defs[] = {
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{ INDEX_op_brcond_i32, { "r", "rJ" } },
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#if TCG_TARGET_REG_BITS == 32
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{ INDEX_op_brcond2_i32, { "r", "r", "rJ", "rJ" } },
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{ INDEX_op_add2_i32, { "r", "r", "r", "r", "rJ", "rJ" } },
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{ INDEX_op_sub2_i32, { "r", "r", "r", "r", "rJ", "rJ" } },
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{ INDEX_op_mulu2_i32, { "r", "r", "r", "rJ" } },
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#endif
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{ INDEX_op_qemu_ld8u, { "r", "L" } },
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