mirror of https://github.com/xemu-project/xemu.git
target-sparc: Implement BMASK/BSHUFFLE.
Signed-off-by: Richard Henderson <rth@twiddle.net>
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@ -140,6 +140,7 @@ DEF_HELPER_FLAGS_3(pdist, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64, i64)
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DEF_HELPER_FLAGS_2(fpack16, TCG_CALL_CONST | TCG_CALL_PURE, i32, i64, i64)
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DEF_HELPER_FLAGS_3(fpack32, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64, i64)
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DEF_HELPER_FLAGS_2(fpackfix, TCG_CALL_CONST | TCG_CALL_PURE, i32, i64, i64)
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DEF_HELPER_FLAGS_3(bshuffle, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64, i64)
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#define VIS_HELPER(name) \
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DEF_HELPER_FLAGS_2(f ## name ## 16, TCG_CALL_CONST | TCG_CALL_PURE, \
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i64, i64, i64) \
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@ -4192,8 +4192,13 @@ static void disas_sparc_insn(DisasContext * dc)
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gen_movl_TN_reg(rd, cpu_dst);
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break;
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case 0x019: /* VIS II bmask */
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// XXX
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goto illegal_insn;
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CHECK_FPU_FEATURE(dc, VIS2);
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cpu_src1 = get_src1(insn, cpu_src1);
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cpu_src2 = get_src1(insn, cpu_src2);
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tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
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tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, cpu_dst, 32, 32);
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gen_movl_TN_reg(rd, cpu_dst);
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break;
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case 0x020: /* VIS I fcmple16 */
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CHECK_FPU_FEATURE(dc, VIS1);
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cpu_src1_64 = gen_load_fpr_D(dc, rs1);
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@ -4314,8 +4319,9 @@ static void disas_sparc_insn(DisasContext * dc)
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gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge);
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break;
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case 0x04c: /* VIS II bshuffle */
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// XXX
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goto illegal_insn;
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CHECK_FPU_FEATURE(dc, VIS2);
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gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_bshuffle);
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break;
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case 0x04d: /* VIS I fexpand */
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CHECK_FPU_FEATURE(dc, VIS1);
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gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fexpand);
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@ -470,3 +470,32 @@ uint32_t helper_fpackfix(uint64_t gsr, uint64_t rs2)
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return ret;
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}
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uint64 helper_bshuffle(uint64_t gsr, uint64_t src1, uint64_t src2)
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{
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union {
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uint64_t ll[2];
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uint8_t b[16];
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} s;
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VIS64 r;
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uint32_t i, mask, host;
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/* Set up S such that we can index across all of the bytes. */
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#ifdef HOST_WORDS_BIGENDIAN
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s.ll[0] = src1;
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s.ll[1] = src2;
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host = 0;
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#else
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s.ll[1] = src1;
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s.ll[0] = src2;
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host = 15;
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#endif
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mask = gsr >> 32;
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for (i = 0; i < 8; ++i) {
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unsigned e = (mask >> (28 - i*4)) & 0xf;
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r.VIS_B64(i) = s.b[e ^ host];
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}
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return r.ll;
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}
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