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target/arm: Tidy do_ldrq 

Use tcg_constant_i32 for passing the simd descriptor,
as this hashed value does not need to be freed.
Rename dofs to doff to match poff.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-78-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2021-05-24 18:03:43 -07:00 committed by Peter Maydell
parent c182c6dbd1
commit 7924d239f4
1 changed files with 4 additions and 9 deletions
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13
target/arm/translate-sve.c
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@ -5580,13 +5580,9 @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
{
unsigned vsz = vec_full_reg_size(s);
TCGv_ptr t_pg;
TCGv_i32 t_desc;
int desc, poff;
int poff;
/* Load the first quadword using the normal predicated load helpers. */
desc = simd_desc(16, 16, zt);
t_desc = tcg_const_i32(desc);
poff = pred_full_reg_offset(s, pg);
if (vsz > 16) {
/*
@ -5611,15 +5607,14 @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
gen_helper_gvec_mem *fn
= ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
fn(cpu_env, t_pg, addr, t_desc);
fn(cpu_env, t_pg, addr, tcg_constant_i32(simd_desc(16, 16, zt)));
tcg_temp_free_ptr(t_pg);
tcg_temp_free_i32(t_desc);
/* Replicate that first quadword. */
if (vsz > 16) {
unsigned dofs = vec_full_reg_offset(s, zt);
tcg_gen_gvec_dup_mem(4, dofs + 16, dofs, vsz - 16, vsz - 16);
int doff = vec_full_reg_offset(s, zt);
tcg_gen_gvec_dup_mem(4, doff + 16, doff, vsz - 16, vsz - 16);
}
}