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target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVA 

The original A.a revision of the AArch64 ARM required that we
force-extend the addresses in these registers from 49 bits.
This language has been loosened via a combination of IMPLEMENTATION
DEFINED and CONSTRAINTED UNPREDICTABLE to allow consideration of
the entire aligned address.

This means that we do not have to consider whether or not FEAT_LVA
is enabled, and decide from which bit an address might need to be
extended.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-03-01 11:59:48 -10:00 committed by Peter Maydell
parent f4ecc01537
commit 777ab8d844
1 changed files with 24 additions and 8 deletions
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32
target/arm/helper.c
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@ -6423,11 +6423,18 @@ static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
ARMCPU *cpu = env_archcpu(env); ARMCPU *cpu = env_archcpu(env);
int i = ri->crm; int i = ri->crm;
/* Bits [63:49] are hardwired to the value of bit [48]; that is, the /*
* register reads and behaves as if values written are sign extended.
* Bits [1:0] are RES0. * Bits [1:0] are RES0.
*
* It is IMPLEMENTATION DEFINED whether [63:49] ([63:53] with FEAT_LVA)
* are hardwired to the value of bit [48] ([52] with FEAT_LVA), or if
* they contain the value written. It is CONSTRAINED UNPREDICTABLE
* whether the RESS bits are ignored when comparing an address.
*
* Therefore we are allowed to compare the entire register, which lets
* us avoid considering whether or not FEAT_LVA is actually enabled.
*/ */
value = sextract64(value, 0, 49) & ~3ULL; value &= ~3ULL;
raw_write(env, ri, value); raw_write(env, ri, value);
hw_watchpoint_update(cpu, i); hw_watchpoint_update(cpu, i);
@ -6473,10 +6480,19 @@ void hw_breakpoint_update(ARMCPU *cpu, int n)
case 0: /* unlinked address match */ case 0: /* unlinked address match */
case 1: /* linked address match */ case 1: /* linked address match */
{ {
/* Bits [63:49] are hardwired to the value of bit [48]; that is, /*
* we behave as if the register was sign extended. Bits [1:0] are * Bits [1:0] are RES0.
* RES0. The BAS field is used to allow setting breakpoints on 16 *
* bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether * It is IMPLEMENTATION DEFINED whether bits [63:49]
* ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit
* of the VA field ([48] or [52] for FEAT_LVA), or whether the
* value is read as written. It is CONSTRAINED UNPREDICTABLE
* whether the RESS bits are ignored when comparing an address.
* Therefore we are allowed to compare the entire register, which
* lets us avoid considering whether FEAT_LVA is actually enabled.
*
* The BAS field is used to allow setting breakpoints on 16-bit
* wide instructions; it is CONSTRAINED UNPREDICTABLE whether
* a bp will fire if the addresses covered by the bp and the addresses * a bp will fire if the addresses covered by the bp and the addresses
* covered by the insn overlap but the insn doesn't start at the * covered by the insn overlap but the insn doesn't start at the
* start of the bp address range. We choose to require the insn and * start of the bp address range. We choose to require the insn and
@ -6489,7 +6505,7 @@ void hw_breakpoint_update(ARMCPU *cpu, int n)
* See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
*/ */
int bas = extract64(bcr, 5, 4); int bas = extract64(bcr, 5, 4);
addr = sextract64(bvr, 0, 49) & ~3ULL; addr = bvr & ~3ULL;
if (bas == 0) { if (bas == 0) {
return; return;
} }