From 7700d2293c085c0481b71cc0f8c04ca20e7bd7d3 Mon Sep 17 00:00:00 2001
From: Richard Henderson <richard.henderson@linaro.org>
Date: Mon, 12 Aug 2024 12:58:44 +1000
Subject: [PATCH] target/i386: Assert MMX and XMM registers in range
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The mmx assert would fire without the fix for #2495.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Link: https://lore.kernel.org/r/20240812025844.58956-4-richard.henderson@linaro.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/emit.c.inc | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index 016dce8146..22a06897fb 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -33,8 +33,13 @@
#define TCG_TARGET_extract_tl_valid TCG_TARGET_extract_i32_valid
#endif
+#define MMX_OFFSET(reg) \
+ ({ assert((reg) >= 0 && (reg) <= 7); \
+ offsetof(CPUX86State, fpregs[reg].mmx); })
-#define ZMM_OFFSET(reg) offsetof(CPUX86State, xmm_regs[reg])
+#define ZMM_OFFSET(reg) \
+ ({ assert((reg) >= 0 && (reg) <= 15); \
+ offsetof(CPUX86State, xmm_regs[reg]); })
typedef void (*SSEFunc_i_ep)(TCGv_i32 val, TCGv_ptr env, TCGv_ptr reg);
typedef void (*SSEFunc_l_ep)(TCGv_i64 val, TCGv_ptr env, TCGv_ptr reg);
@@ -168,7 +173,7 @@ static int vector_elem_offset(X86DecodedOp *op, MemOp ot, int n)
static void compute_mmx_offset(X86DecodedOp *op)
{
if (!op->has_ea) {
- op->offset = offsetof(CPUX86State, fpregs[op->n].mmx) + mmx_offset(op->ot);
+ op->offset = MMX_OFFSET(op->n) + mmx_offset(op->ot);
} else {
op->offset = offsetof(CPUX86State, mmx_t0) + mmx_offset(op->ot);
}