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target/riscv: Split the Hypervisor execute load helpers 

Split the hypervisor execute load functions into two seperate functions.
This avoids us having to pass the memop to the C helper functions.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 5b1550f0faa3c435cc77f3c1ae811dea98ab9e36.1604464950.git.alistair.francis@wdc.com
This commit is contained in:
Alistair Francis 2020-11-03 20:43:34 -08:00
parent 743077b35b
commit 7687537ab0
3 changed files with 16 additions and 41 deletions
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3
target/riscv/helper.h
View File

@ -81,7 +81,8 @@ DEF_HELPER_1(tlb_flush, void, env)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_1(hyp_tlb_flush, void, env)
DEF_HELPER_1(hyp_gvma_tlb_flush, void, env)
DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl)
DEF_HELPER_2(hyp_hlvx_hu, tl, env, tl)
DEF_HELPER_2(hyp_hlvx_wu, tl, env, tl)
#endif
/* Vector functions */

20
target/riscv/insn_trans/trans_rvh.c.inc
View File

@ -277,20 +277,16 @@ static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a)
#ifndef CONFIG_USER_ONLY
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv mem_idx = tcg_temp_new();
TCGv memop = tcg_temp_new();
check_access(ctx);
gen_get_gpr(t0, a->rs1);
tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
tcg_gen_movi_tl(memop, MO_TEUW);
gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop);
gen_helper_hyp_hlvx_hu(t1, cpu_env, t0);
gen_set_gpr(a->rd, t1);
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(mem_idx);
tcg_temp_free(memop);
return true;
#else
return false;
@ -303,20 +299,16 @@ static bool trans_hlvx_wu(DisasContext *ctx, arg_hlvx_wu *a)
#ifndef CONFIG_USER_ONLY
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv mem_idx = tcg_temp_new();
TCGv memop = tcg_temp_new();
check_access(ctx);
gen_get_gpr(t0, a->rs1);
tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
tcg_gen_movi_tl(memop, MO_TEUL);
gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop);
gen_helper_hyp_hlvx_wu(t1, cpu_env, t0);
gen_set_gpr(a->rd, t1);
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(mem_idx);
tcg_temp_free(memop);
return true;
#else
return false;

34
target/riscv/op_helper.c
View File

@ -227,36 +227,18 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env)
helper_hyp_tlb_flush(env);
}
target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address,
target_ulong attrs, target_ulong memop)
target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong address)
{
if (env->priv == PRV_M ||
(env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
(env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
get_field(env->hstatus, HSTATUS_HU))) {
target_ulong pte;
int mmu_idx = cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
int mmu_idx = cpu_mmu_index(env, true) | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
switch (memop) {
case MO_TEUW:
pte = cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC());
break;
case MO_TEUL:
pte = cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC());
break;
default:
g_assert_not_reached();
}
return cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC());
}
return pte;
}
target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong address)
{
int mmu_idx = cpu_mmu_index(env, true) | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
if (riscv_cpu_virt_enabled(env)) {
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
} else {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
return 0;
return cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC());
}
#endif /* !CONFIG_USER_ONLY */