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Move FP TNs to cpu env. 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4728 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2008-06-11 10:39:48 +00:00
parent ae45d3693b
commit 764dfc3fa0
3 changed files with 27 additions and 26 deletions
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11
target-mips/cpu.h
View File

@ -70,11 +70,6 @@ typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
struct CPUMIPSFPUContext { struct CPUMIPSFPUContext {
/* Floating point registers */ /* Floating point registers */
fpr_t fpr[32]; fpr_t fpr[32];
#ifndef USE_HOST_FLOAT_REGS
fpr_t ft0;
fpr_t ft1;
fpr_t ft2;
#endif
float_status fp_status; float_status fp_status;
/* fpu implementation/revision register (fir) */ /* fpu implementation/revision register (fir) */
uint32_t fcr0; uint32_t fcr0;
@ -148,6 +143,12 @@ struct CPUMIPSState {
#if TARGET_LONG_BITS > HOST_LONG_BITS #if TARGET_LONG_BITS > HOST_LONG_BITS
target_ulong t0; target_ulong t0;
target_ulong t1; target_ulong t1;
#endif
/* temporary hack for FP globals */
#ifndef USE_HOST_FLOAT_REGS
fpr_t ft0;
fpr_t ft1;
fpr_t ft2;
#endif #endif
target_ulong HI[MIPS_TC_MAX][MIPS_DSP_ACC]; target_ulong HI[MIPS_TC_MAX][MIPS_DSP_ACC];
target_ulong LO[MIPS_TC_MAX][MIPS_DSP_ACC]; target_ulong LO[MIPS_TC_MAX][MIPS_DSP_ACC];

36
target-mips/exec.h
View File

@ -21,24 +21,24 @@ register target_ulong T1 asm(AREG2);
#if defined (USE_HOST_FLOAT_REGS) #if defined (USE_HOST_FLOAT_REGS)
#error "implement me." #error "implement me."
#else #else
#define FDT0 (env->fpu->ft0.fd) #define FDT0 (env->ft0.fd)
#define FDT1 (env->fpu->ft1.fd) #define FDT1 (env->ft1.fd)
#define FDT2 (env->fpu->ft2.fd) #define FDT2 (env->ft2.fd)
#define FST0 (env->fpu->ft0.fs[FP_ENDIAN_IDX]) #define FST0 (env->ft0.fs[FP_ENDIAN_IDX])
#define FST1 (env->fpu->ft1.fs[FP_ENDIAN_IDX]) #define FST1 (env->ft1.fs[FP_ENDIAN_IDX])
#define FST2 (env->fpu->ft2.fs[FP_ENDIAN_IDX]) #define FST2 (env->ft2.fs[FP_ENDIAN_IDX])
#define FSTH0 (env->fpu->ft0.fs[!FP_ENDIAN_IDX]) #define FSTH0 (env->ft0.fs[!FP_ENDIAN_IDX])
#define FSTH1 (env->fpu->ft1.fs[!FP_ENDIAN_IDX]) #define FSTH1 (env->ft1.fs[!FP_ENDIAN_IDX])
#define FSTH2 (env->fpu->ft2.fs[!FP_ENDIAN_IDX]) #define FSTH2 (env->ft2.fs[!FP_ENDIAN_IDX])
#define DT0 (env->fpu->ft0.d) #define DT0 (env->ft0.d)
#define DT1 (env->fpu->ft1.d) #define DT1 (env->ft1.d)
#define DT2 (env->fpu->ft2.d) #define DT2 (env->ft2.d)
#define WT0 (env->fpu->ft0.w[FP_ENDIAN_IDX]) #define WT0 (env->ft0.w[FP_ENDIAN_IDX])
#define WT1 (env->fpu->ft1.w[FP_ENDIAN_IDX]) #define WT1 (env->ft1.w[FP_ENDIAN_IDX])
#define WT2 (env->fpu->ft2.w[FP_ENDIAN_IDX]) #define WT2 (env->ft2.w[FP_ENDIAN_IDX])
#define WTH0 (env->fpu->ft0.w[!FP_ENDIAN_IDX]) #define WTH0 (env->ft0.w[!FP_ENDIAN_IDX])
#define WTH1 (env->fpu->ft1.w[!FP_ENDIAN_IDX]) #define WTH1 (env->ft1.w[!FP_ENDIAN_IDX])
#define WTH2 (env->fpu->ft2.w[!FP_ENDIAN_IDX]) #define WTH2 (env->ft2.w[!FP_ENDIAN_IDX])
#endif #endif
#include "cpu.h" #include "cpu.h"

6
target-mips/translate.c
View File

@ -7386,9 +7386,9 @@ void fpu_dump_state(CPUState *env, FILE *f,
fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n", fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n",
env->fpu->fcr0, env->fpu->fcr31, is_fpu64, env->fpu->fp_status, env->fpu->fcr0, env->fpu->fcr31, is_fpu64, env->fpu->fp_status,
get_float_exception_flags(&env->fpu->fp_status)); get_float_exception_flags(&env->fpu->fp_status));
fpu_fprintf(f, "FT0: "); printfpr(&env->fpu->ft0); fpu_fprintf(f, "FT0: "); printfpr(&env->ft0);
fpu_fprintf(f, "FT1: "); printfpr(&env->fpu->ft1); fpu_fprintf(f, "FT1: "); printfpr(&env->ft1);
fpu_fprintf(f, "FT2: "); printfpr(&env->fpu->ft2); fpu_fprintf(f, "FT2: "); printfpr(&env->ft2);
for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) { for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
fpu_fprintf(f, "%3s: ", fregnames[i]); fpu_fprintf(f, "%3s: ", fregnames[i]);
printfpr(&env->fpu->fpr[i]); printfpr(&env->fpu->fpr[i]);