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target/loongarch: Implement xvneg 

This patch includes:
- XVNEG.{B/H/W/D}.

Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914022645.1151356-18-gaosong@loongson.cn>
This commit is contained in:
Song Gao 2023-09-14 10:26:05 +08:00
parent 342004214b
commit 760f964717
No known key found for this signature in database
GPG Key ID: 40A2FFF239263EDF
3 changed files with 30 additions and 4 deletions
target/loongarch
disas.c
insn_trans
trans_vec.c.inc
insns.decode

10
target/loongarch/disas.c
View File

@ -1718,6 +1718,11 @@ static void output_vv_i_x(DisasContext *ctx, arg_vv_i *a, const char *mnemonic)
output(ctx, mnemonic, "x%d, x%d, 0x%x", a->vd, a->vj, a->imm);
}
static void output_vv_x(DisasContext *ctx, arg_vv *a, const char *mnemonic)
{
output(ctx, mnemonic, "x%d, x%d", a->vd, a->vj);
}
INSN_LASX(xvadd_b, vvv)
INSN_LASX(xvadd_h, vvv)
INSN_LASX(xvadd_w, vvv)
@ -1738,6 +1743,11 @@ INSN_LASX(xvsubi_hu, vv_i)
INSN_LASX(xvsubi_wu, vv_i)
INSN_LASX(xvsubi_du, vv_i)
INSN_LASX(xvneg_b, vv)
INSN_LASX(xvneg_h, vv)
INSN_LASX(xvneg_w, vv)
INSN_LASX(xvneg_d, vv)
INSN_LASX(xvreplgr2vr_b, vr)
INSN_LASX(xvreplgr2vr_h, vr)
INSN_LASX(xvreplgr2vr_w, vr)

19
target/loongarch/insn_trans/trans_vec.c.inc
View File

@ -223,6 +223,10 @@ static bool gvec_vv_vl(DisasContext *ctx, arg_vv *a,
uint32_t vd_ofs = vec_full_offset(a->vd);
uint32_t vj_ofs = vec_full_offset(a->vj);
if (!check_vec(ctx, oprsz)) {
return true;
}
func(mop, vd_ofs, vj_ofs, oprsz, ctx->vl / 8);
return true;
}
@ -232,13 +236,16 @@ static bool gvec_vv(DisasContext *ctx, arg_vv *a, MemOp mop,
void (*func)(unsigned, uint32_t, uint32_t,
uint32_t, uint32_t))
{
if (!check_vec(ctx, 16)) {
return true;
}
return gvec_vv_vl(ctx, a, 16, mop, func);
}
static bool gvec_xx(DisasContext *ctx, arg_vv *a, MemOp mop,
void (*func)(unsigned, uint32_t, uint32_t,
uint32_t, uint32_t))
{
return gvec_vv_vl(ctx, a, 32, mop, func);
}
static bool gvec_vv_i_vl(DisasContext *ctx, arg_vv_i *a,
uint32_t oprsz, MemOp mop,
void (*func)(unsigned, uint32_t, uint32_t,
@ -383,6 +390,10 @@ TRANS(vneg_b, LSX, gvec_vv, MO_8, tcg_gen_gvec_neg)
TRANS(vneg_h, LSX, gvec_vv, MO_16, tcg_gen_gvec_neg)
TRANS(vneg_w, LSX, gvec_vv, MO_32, tcg_gen_gvec_neg)
TRANS(vneg_d, LSX, gvec_vv, MO_64, tcg_gen_gvec_neg)
TRANS(xvneg_b, LASX, gvec_xx, MO_8, tcg_gen_gvec_neg)
TRANS(xvneg_h, LASX, gvec_xx, MO_16, tcg_gen_gvec_neg)
TRANS(xvneg_w, LASX, gvec_xx, MO_32, tcg_gen_gvec_neg)
TRANS(xvneg_d, LASX, gvec_xx, MO_64, tcg_gen_gvec_neg)
TRANS(vsadd_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_ssadd)
TRANS(vsadd_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_ssadd)

5
target/loongarch/insns.decode
View File

@ -1320,6 +1320,11 @@ xvsubi_hu 0111 01101000 11001 ..... ..... ..... @vv_ui5
xvsubi_wu 0111 01101000 11010 ..... ..... ..... @vv_ui5
xvsubi_du 0111 01101000 11011 ..... ..... ..... @vv_ui5
xvneg_b 0111 01101001 11000 01100 ..... ..... @vv
xvneg_h 0111 01101001 11000 01101 ..... ..... @vv
xvneg_w 0111 01101001 11000 01110 ..... ..... @vv
xvneg_d 0111 01101001 11000 01111 ..... ..... @vv
xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr
xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr
xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr