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target/xtensa: implement DIWBUI.P opcode 

This is a recent addition to the set of data cache opcodes.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2019-04-14 14:02:17 -07:00
parent 4d04ea35b3
commit 75eed0e5f7
3 changed files with 12 additions and 0 deletions
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1
target/xtensa/cpu.h
View File

@ -466,6 +466,7 @@ struct XtensaConfig {
unsigned icache_ways; unsigned icache_ways;
unsigned dcache_ways; unsigned dcache_ways;
unsigned dcache_line_bytes;
uint32_t memctl_mask; uint32_t memctl_mask;
XtensaMemory instrom; XtensaMemory instrom;

1
target/xtensa/overlay_tool.h
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@ -425,6 +425,7 @@
#define CACHE_SECTION \ #define CACHE_SECTION \
.icache_ways = XCHAL_ICACHE_WAYS, \ .icache_ways = XCHAL_ICACHE_WAYS, \
.dcache_ways = XCHAL_DCACHE_WAYS, \ .dcache_ways = XCHAL_DCACHE_WAYS, \
.dcache_line_bytes = XCHAL_DCACHE_LINESIZE, \
.memctl_mask = \ .memctl_mask = \
(XCHAL_ICACHE_SIZE ? MEMCTL_IUSEWAYS_MASK : 0) | \ (XCHAL_ICACHE_SIZE ? MEMCTL_IUSEWAYS_MASK : 0) | \
(XCHAL_DCACHE_SIZE ? \ (XCHAL_DCACHE_SIZE ? \

10
target/xtensa/translate.c
View File

@ -1620,6 +1620,12 @@ static void translate_depbits(DisasContext *dc, const OpcodeArg arg[],
arg[2].imm, arg[3].imm); arg[2].imm, arg[3].imm);
} }
static void translate_diwbuip(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
tcg_gen_addi_i32(arg[0].out, arg[0].in, dc->config->dcache_line_bytes);
}
static bool test_ill_entry(DisasContext *dc, const OpcodeArg arg[], static bool test_ill_entry(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
@ -3097,6 +3103,10 @@ static const XtensaOpcodeOps core_ops[] = {
.name = "diwbi", .name = "diwbi",
.translate = translate_nop, .translate = translate_nop,
.op_flags = XTENSA_OP_PRIVILEGED, .op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "diwbui.p",
.translate = translate_diwbuip,
.op_flags = XTENSA_OP_PRIVILEGED,
}, { }, {
.name = "dpfl", .name = "dpfl",
.translate = translate_dcache, .translate = translate_dcache,