mirror of https://github.com/xemu-project/xemu.git
kvm: i386: fix LAPIC TSC deadline timer save/restore
The configuration of the timer represented by MSR_IA32_TSCDEADLINE depends on: - APIC LVT Timer register. - TSC value. Change the order to respect the dependency. Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -1073,6 +1073,26 @@ static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
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entry->data = value;
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entry->data = value;
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}
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}
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static int kvm_put_tscdeadline_msr(X86CPU *cpu)
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{
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CPUX86State *env = &cpu->env;
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struct {
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struct kvm_msrs info;
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struct kvm_msr_entry entries[1];
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} msr_data;
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struct kvm_msr_entry *msrs = msr_data.entries;
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if (!has_msr_tsc_deadline) {
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return 0;
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}
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kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
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msr_data.info.nmsrs = 1;
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return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
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}
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static int kvm_put_msrs(X86CPU *cpu, int level)
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static int kvm_put_msrs(X86CPU *cpu, int level)
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{
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{
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CPUX86State *env = &cpu->env;
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CPUX86State *env = &cpu->env;
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@ -1096,9 +1116,6 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
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if (has_msr_tsc_adjust) {
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if (has_msr_tsc_adjust) {
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kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
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kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
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}
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}
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if (has_msr_tsc_deadline) {
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kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
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}
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if (has_msr_misc_enable) {
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if (has_msr_misc_enable) {
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kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
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kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
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env->msr_ia32_misc_enable);
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env->msr_ia32_misc_enable);
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@ -1808,6 +1825,12 @@ int kvm_arch_put_registers(CPUState *cpu, int level)
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return ret;
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return ret;
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}
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}
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}
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}
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ret = kvm_put_tscdeadline_msr(x86_cpu);
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if (ret < 0) {
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return ret;
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}
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ret = kvm_put_vcpu_events(x86_cpu, level);
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ret = kvm_put_vcpu_events(x86_cpu, level);
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if (ret < 0) {
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if (ret < 0) {
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return ret;
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return ret;
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